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authorFelix Held <felix-coreboot@felixheld.de>2021-04-08 22:25:19 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-04-21 22:12:06 +0000
commitd0b5164cd0980c078323792bd47c3aee6438e9b8 (patch)
tree950c09e5e539c8de744e1f6547c82dd9dbd9eaec /src/device/pci_ops.c
parent02bfbf44305d1c7d562b9425da53d43d398061cd (diff)
soc/amd/cezanne: add downcoring and SMT disable settings to devicetree
BUG=b:184162768 TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_ops.c')
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