diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-08-06 12:10:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-09 08:49:19 +0000 |
| commit | cb5304bc0a64b7d7235e3d48abdb8a4cf499c3a8 (patch) | |
| tree | 3767f562a3e6fee0df5d7e159d7618664e006d96 /src/device/pci_ops.c | |
| parent | 60828b7fa9ad888aee0c7dfff17b5b6a507f2469 (diff) | |
cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore
guard against this.
Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/device/pci_ops.c')
0 files changed, 0 insertions, 0 deletions