diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-01 16:49:09 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-23 20:39:44 +0000 |
commit | 7bdedcdc338e5043f9670790a4333260b63087aa (patch) | |
tree | 2a02bc0ddbf636f58c785ae64705cf675e6e2701 /src/device/pci_ops.c | |
parent | 88e9c5af574130483de24cdc1e2328e0dd622793 (diff) |
soc/intel/skylake: lock AES-NI MSR
Lock AES-NI register to prevent unintended disabling, as suggested by the
MSR datasheet.
Successfully tested by reading the MSR on X11SSM-F
Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35188
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_ops.c')
0 files changed, 0 insertions, 0 deletions