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authorGaggery Tsai <gaggery.tsai@intel.com>2022-02-17 11:37:59 -0800
committerFelix Held <felix-coreboot@felixheld.de>2022-03-02 13:09:28 +0000
commit9d0fc3f39650d5b3bc24507d8c3e053074bf370d (patch)
tree54dbac86c3bccb4a22f06f59b57e242989bd24aa /src/device/pci_device.c
parent7a7a533725904c66e783ce57f04aae07a3dd91c9 (diff)
mb/google/brya/var/vell: Remove Rcomp settings
This patch removes Rcomp settings. In MRC design, it checks if the Rcomp settings from the board is 0 or null, if so, it uses the recommended Rcomp values. Otherwise, it uses the Rcomp settings passed from the UPD. From the change history of MRC, we're chasing a moving target. This RCOMP setting in coreboot is an old setting while the Rcomp settins in MRC are optimized settings. Moving forward, if there is a new stepping, it might be changed again which increases the maintenance effort in coreboot. IMHO, we should let MRC to set the optimized RCOMP values for the design. BUG=b:219378758 TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are filled properly by MRC. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device/pci_device.c')
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