diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2024-07-29 13:37:36 -0600 |
|---|---|---|
| committer | Jon Murphy <jpmurphy@google.com> | 2024-07-31 14:11:30 +0000 |
| commit | fa66d33336fcf4358c1bacd84ae9427f8dfb59ba (patch) | |
| tree | de01edf8b12b6558516fd02e833ebb844d91da25 /src/device/pci_class.c | |
| parent | 8200a9ac387ca35d93b307ff01038d686c9281e4 (diff) | |
soc/intel/adl: Update DCACHE_BSP_STACK_SIZE
During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.
BUG=None
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/device/pci_class.c')
0 files changed, 0 insertions, 0 deletions