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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-03-23 12:28:56 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-30 23:55:15 +0000 |
| commit | abe0d810f00927f1589e6f7909e898c211a30319 (patch) | |
| tree | 220bb58a759537e6050aa83017dae58bef67bdb7 /src/device/i2c.c | |
| parent | e3ee917cba7329419761947364a655639f63d7af (diff) | |
soc/intel/alderlake: Log CSE RO write protection info for ADL
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
TEST=Verify the write protection details on Gimble.
Excerpt from Gimble coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device/i2c.c')
0 files changed, 0 insertions, 0 deletions