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| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2021-12-24 20:45:00 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-04 16:15:31 +0000 |
| commit | f1edd4fe6070f961fc150670593bc3f22e6f8a7d (patch) | |
| tree | bfe660a33afb9429f388ff0dbb39ffa886e812cd /src/device/gpio.c | |
| parent | fc86f8bf27ea41f9c9e07575883210bfb2092db4 (diff) | |
mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.
BUG=b:211914322
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.
Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device/gpio.c')
0 files changed, 0 insertions, 0 deletions