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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-09-11 10:03:08 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-15 11:53:34 +0000
commitded91fffb833823ea7d71654c1e10696eba0d419 (patch)
tree34c720d4e0f5d8f794a61e8cda10e7c7939c0b5c /src/device/dram
parent694d18a6418bea102850e1695ad4d71fe831a113 (diff)
arch/riscv: Configure delegation only if S-mode is supported
On the FU540 the bootblock runs on a core without lesser privilege modes, so the medeleg/mideleg CSRs are not implemented on that core, leading to a CPU exception when these CSRs are accessed. Configure medeleg/mideleg only if the misa register indicates that S-mode is implemented on the executing RISC-V core. Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25791 Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Johanna Schander <coreboot@mimoja.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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