diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-10-26 20:46:21 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-11-11 09:10:10 +0000 |
| commit | 6de8b424824069345714001766b389f0b992df8e (patch) | |
| tree | ff3b4a308ce58213e068e7709584b3fdb04b98f5 /src/device/dram/ddr3.c | |
| parent | 9a3bde0581a574956dd57ca24683c41ac7e0edfc (diff) | |
arch/x86: Refactor the SMBIOS type 17 write function
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).
Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Unknown
....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Row Of Chips
....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device/dram/ddr3.c')
| -rw-r--r-- | src/device/dram/ddr3.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 0a32d02de9..b99730d45b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, switch (info->dimm_type) { case SPD_DDR3_DIMM_TYPE_SO_DIMM: - dimm->mod_type = SPD_SODIMM; + dimm->mod_type = DDR3_SPD_SODIMM; break; case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: - dimm->mod_type = SPD_72B_SO_CDIMM; + dimm->mod_type = DDR3_SPD_72B_SO_CDIMM; break; case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = SPD_72B_SO_RDIMM; + dimm->mod_type = DDR3_SPD_72B_SO_RDIMM; break; case SPD_DDR3_DIMM_TYPE_UDIMM: - dimm->mod_type = SPD_UDIMM; + dimm->mod_type = DDR3_SPD_UDIMM; break; case SPD_DDR3_DIMM_TYPE_RDIMM: - dimm->mod_type = SPD_RDIMM; + dimm->mod_type = DDR3_SPD_RDIMM; break; case SPD_DDR3_DIMM_TYPE_UNDEFINED: default: |