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author | Angel Pons <th3fanbus@gmail.com> | 2020-11-13 13:31:58 +0100 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 23:03:26 +0000 |
commit | 7f1363d9b4672c79b2538dcf9757cbb036aaf3e3 (patch) | |
tree | 8c6c1d63b0c50024db1e32665eccea30dfe64890 /src/device/dram/ddr2.c | |
parent | f999748fb3d75e16d0f1cfc44876bd02cc1280ac (diff) |
nb/intel/sandybridge: Program MR2 shadow register
This register must be programmed if Self-Refresh Temperature range is
enabled in MR2 (bit 7). Because the memory controller needs to reprogram
MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It
also needs to know about mirrored ranks to correctly issue MRS commands.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/device/dram/ddr2.c')
0 files changed, 0 insertions, 0 deletions