diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-06-07 08:55:14 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-09 15:10:34 +0000 |
| commit | f892b85e18bfead6ed1f135e50ed4e9544553278 (patch) | |
| tree | 4da60b66b8b32b2f226744ba675cedb0e816b742 /src/device/dram/Makefile.inc | |
| parent | eca3e6278abd37da60cd68bb3705ce1cc01d4f47 (diff) | |
device/dram: Add LPDDR4 utilities
Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts.
Fill in lpddr4_speeds using JDEC 209-4C table 210.
LPDDR4 SPD decoding utilities are not included since there isn't
a present need.
BUG=b:184124605
TEST=Build and run on guybrush
Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/device/dram/Makefile.inc')
| -rw-r--r-- | src/device/dram/Makefile.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 69fcfa8844..b91b128f85 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1,3 +1,3 @@ -romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c +romstage-y += lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c -ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c spd.c +ramstage-y += lpddr4.c ddr4.c ddr3.c ddr2.c ddr_common.c spd.c |