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authorAngel Pons <th3fanbus@gmail.com>2020-07-23 02:37:12 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-28 10:54:29 +0000
commit598ec6af9814a0b94fcbbafa9dde2197185ad4c3 (patch)
treebeb1a4cac769f6caa0b001fc8f4bfec8f6665612 /src/device/azalia_device.c
parentb82b4314ad32dcdb02cb5db1efcda3417aa8fe5d (diff)
nb/intel/haswell: Enable DMI ASPM
On Haswell platforms, the processor and the PCH are two separate dies, and communicate through a high-speed bus. This is DMI (Direct Media Interface) on traditional two-package platforms, but single-package Haswell LP variants use OPI (On-Package Interconnect) instead. Since OPI is not routed through the mainboard, most link parameters are static and cannot be changed. OPI self-initializes on boot, anyway. However, DMI needs to be initialized in firmware. On Haswell, the MRC initializes the physical DMI link, but things like topology and power management need to be configured as well. And we don't do that properly. We enable ASPM on the PCH side of the DMI link, but not on the SA side. Both sides need to use the same settings, so enable DMI ASPM on the SA. Clearing the error status bits needs to be done on all Haswell variants. Tested on Asrock B85M Pro4, still boots. Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/device/azalia_device.c')
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