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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-02-14 12:45:09 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-09 11:29:45 +0200
commit4c686f2106a33e7a452bec163c178724a0313616 (patch)
treee47f615d45fe9ca7860fb60fc2951c53a16166f1 /src/device/Kconfig
parentafa7b13b9355b3df3da7606d434cb8b450316ab9 (diff)
OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/device/Kconfig')
-rw-r--r--src/device/Kconfig29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index eaa0c042f7..932b4de540 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -237,6 +237,35 @@ config PCIEXP_ASPM
config PCI_BUS_SEGN_BITS
int
default 0
+
+config EARLY_PCI_BRIDGE
+ bool "Early PCI bridge"
+ depends on PCI
+ default n
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system.
+
+ This option enables static configuration for a single pre-defined
+ PCI bridge function on bus 0.
+
+if EARLY_PCI_BRIDGE
+
+config EARLY_PCI_BRIDGE_DEVICE
+ hex "bridge device"
+ default 0x0
+
+config EARLY_PCI_BRIDGE_FUNCTION
+ hex "bridge function"
+ default 0x0
+
+config EARLY_PCI_MMIO_BASE
+ hex "MMIO window base"
+ default 0x0
+
+endif # EARLY_PCI_BRIDGE
+
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