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authorFelix Held <felix-coreboot@felixheld.de>2023-09-12 14:18:49 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-09-29 20:20:50 +0000
commitff4d6be9f99c34242140e965f1ed82240d67198c (patch)
tree0a4cb2ea2539d4413eb5e1ec39d35a7dee95724d /src/cpu
parent49c4584669cb854a1108b4ad9ac286aa607245c5 (diff)
*/include/cpu: use unsigned int for number of address bits
The number of physical address bits and reserved address bits shouldn't ever be negative, so change the return type of cpu_phys_address_size, get_reserved_phys_addr_bits, and get_tme_keyid_bits from int to unsigned int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e67db6bf0c38f743b50e7273449cc028de13a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/78072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/common/common_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index ff00f0247f..55bc59eb75 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -248,7 +248,7 @@ bool is_tme_supported(void)
* configured in the MSRs according to the capabilities and platform
* configuration. For instance, after FSP-M.
*/
-static int get_tme_keyid_bits(void)
+static unsigned int get_tme_keyid_bits(void)
{
msr_t msr;
@@ -256,7 +256,7 @@ static int get_tme_keyid_bits(void)
return msr.hi & TME_ACTIVATE_HI_KEYID_BITS_MASK;
}
-int get_reserved_phys_addr_bits(void)
+unsigned int get_reserved_phys_addr_bits(void)
{
if (!is_tme_supported())
return 0;