summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2022-10-18 19:48:41 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-10-20 16:41:53 +0000
commitf1a03b1d6d9c02f4c1db1cc6c11e772ce0c6ca56 (patch)
tree1246bc0a85878dafa71f9c3cd4fab13c64b29764 /src/cpu
parentc6e4cc8873791b1c112ef8bd392a1aab1e940246 (diff)
soc/amd/stoneyridge: initialize GPIOs for serial console
Initialize the two GPIOs of the SoC UART if it's used for serial console to be sure that the I/O mux is configured correctly without having to rely on the bootblock_mainboard_early_init call to do this. This brings Stoneyridge more in line with the other AMD SoCs. Since this code will be factored out to the common AMD SoC code in a follow-up patch, the function prototype is added to southbridge.h instead of creating a new uart.h header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions