diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-02-02 18:49:53 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-03-28 15:22:34 +0000 |
| commit | ee83be4d753ae128b53dd306b380c4a6dfd739e5 (patch) | |
| tree | a22c88456df0343f37e7dbaf35627857ae6d9fb8 /src/cpu | |
| parent | 34684caad56a489b26c0cf7f5f7f98cff7dc72c5 (diff) | |
cpu/x86: Link page tables in stage if possible
When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.
TEST: Booted to payload on google/vilbox and qemu/q35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/cpu/x86/64bit/Makefile.mk | 4 | ||||
| -rw-r--r-- | src/cpu/x86/64bit/entry64.inc | 2 | ||||
| -rw-r--r-- | src/cpu/x86/64bit/mode_switch.S | 2 | ||||
| -rw-r--r-- | src/cpu/x86/64bit/mode_switch2.S | 2 | ||||
| -rw-r--r-- | src/cpu/x86/64bit/pt.S | 2 |
8 files changed, 11 insertions, 7 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 2e4d9c8074..227ddf4c22 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ addrsize_set_high: subl $4, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 578bf03afd..9485cd44fb 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ end_microcode_update: andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 32fddd6810..1cb422dbfc 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ fill_cache: subl $4, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk index a8dc1a286a..b24e4d7de0 100644 --- a/src/cpu/x86/64bit/Makefile.mk +++ b/src/cpu/x86/64bit/Makefile.mk @@ -9,13 +9,15 @@ else PAGETABLE_SRC := pt.S endif +all_x86-y += $(PAGETABLE_SRC) + # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/$(PAGETABLE_SRC) $(obj)/config.h $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0 $(OBJCOPY_ramstage) -Obinary -j .rodata $@.tmp $@ rm $@.tmp -cbfs-files-y += pagetables +cbfs-files-$(CONFIG_PAGE_TABLES_IN_CBFS) += pagetables pagetables-file := $(objcbfs)/pt pagetables-type := raw pagetables-compression := none diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 878f310843..52da6037d5 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -11,9 +11,11 @@ #if ENV_X86_64 .code32 +#if CONFIG(PAGE_TABLES_IN_CBFS) #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! #endif +#endif #include <cpu/x86/msr.h> #if defined(__RAMSTAGE__) diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index 01fe003cb1..9555cefbbb 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -44,7 +44,7 @@ protected_mode_call_wrapper: movl %eax, %ebx /* Preserves ebx */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE /* Place return value in rax */ movl %ebx, %eax diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 1807d2e404..18c6425d7f 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ long_mode_call_3arg: mov %esp, %ebp /* Enter long mode, preserves ebx */ - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE /* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index b105528e5e..67e4b1b8bf 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -18,7 +18,7 @@ #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) .global PM4LE -.align 32 +.align 4096 PM4LE: .quad _GEN_DIR(PDPE_table) |