add .h files for common exynos 5

Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1926
Tested-by: build bot (Jenkins)

14 files changed, 1220 insertions, 0 deletions

diff --git a/src/cpu/samsung/exynos5-common/adc.h b/src/cpu/samsung/exynos5-common/adc.h
new file mode 100644
index 0000000000..dc905d14d9
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/adc.h
@@ -0,0 +1,42 @@
+/*
+ *  Copyright (C) 2010 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_COMMON_ADC_H_
+#define __ASM_ARM_ARCH_COMMON_ADC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_adc {
+	unsigned int adccon;
+	unsigned int adctsc;
+	unsigned int adcdly;
+	unsigned int adcdat0;
+	unsigned int adcdat1;
+	unsigned int adcupdn;
+	unsigned int adcclrint;
+	unsigned int adcmux;
+	unsigned int adcclrintpndnup;
+};
+#endif
+
+#endif /* __ASM_ARM_ARCH_COMMON_ADC_H_ */
diff --git a/src/cpu/samsung/exynos5-common/clk.h b/src/cpu/samsung/exynos5-common/clk.h
new file mode 100644
index 0000000000..0178f88ff2
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/clk.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2012 The Chromium Authors
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXYNOS_COMMON_CLK_H_
+#define __EXYNOS_COMMON_CLK_H_
+
+#include <types.h>
+#include <stdint.h>
+
+enum periph_id;
+
+#define APLL	0
+#define MPLL	1
+#define EPLL	2
+#define HPLL	3
+#define VPLL	4
+#define BPLL	5
+
+enum pll_src_bit {
+	SRC_MPLL = 6,
+	SRC_EPLL,
+	SRC_VPLL,
+};
+
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+	s8 src_bit;    /* offset in register to clock source field */
+	s8 n_src_bits; /* number of bits in 'src_bit' field */
+	s8 div_bit;
+	s8 prediv_bit;
+};
+
+/* FIXME(dhendrix) conflicts with stp-common/clk.h */
+#if 0
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+void set_mmc_clk(int dev_index, unsigned int div);
+#endif
+
+/**
+ * get the clk frequency of the required peripherial
+ *
+ * @param peripherial	Peripherial id
+ *
+ * @return frequency of the peripherial clk
+ */
+unsigned long clock_get_periph_rate(enum periph_id peripheral);
+
+#endif
diff --git a/src/cpu/samsung/exynos5-common/cpu.h b/src/cpu/samsung/exynos5-common/cpu.h
new file mode 100644
index 0000000000..e68de8688f
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/cpu.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS_COMMON_CPU_H
+#define _EXYNOS_COMMON_CPU_H
+
+#include <cpu/samsung/s5p-common/cpu.h>
+
+#define DEVICE_NOT_AVAILABLE		0
+
+#define EXYNOS_PRO_ID			0x10000000
+
+/* Address of address of function that copys data from SD or MMC */
+#define EXYNOS_COPY_MMC_FNPTR_ADDR	0x02020030
+
+/* Address of address of function that copys data from SPI */
+#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
+
+/* Address of address of function that copys data through USB */
+#define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
+
+/* Boot mode values */
+#define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
+
+#define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
+
+#define EXYNOS_I2C_SPACING		0x10000
+
+enum boot_mode {
+	/*
+	 * Assign the OM pin values for respective boot modes.
+	 * Exynos4 does not support spi boot and the mmc boot OM
+	 * pin values are the same across Exynos4 and Exynos5.
+	 */
+	BOOT_MODE_MMC = 4,
+	BOOT_MODE_SERIAL = 20,
+	/* Boot based on Operating Mode pin settings */
+	BOOT_MODE_OM = 32,
+	BOOT_MODE_USB,		/* Boot using USB download */
+};
+
+#if 0
+/**
+ * Get the U-boot size for SPL copy functions
+ *
+ * @return size of U-Boot code/data that needs to be loaded by the SPL stage
+ */
+unsigned int exynos_get_uboot_size(void);
+#endif
+
+/**
+ * Get the boot device containing BL1, BL2 (SPL) and U-boot
+ *
+ * @return boot device
+ */
+enum boot_mode exynos_get_boot_device(void);
+
+/**
+ * Check if a wakeup is permitted.
+ *
+ * On some boards we need to look at a special GPIO to ensure that the wakeup
+ * from sleep was valid.  If the wakeup is not valid we need to go through a
+ * full reset.
+ *
+ * The default implementation of this function allows all wakeups.
+ *
+ * @return 1 if wakeup is permitted; 0 otherwise
+ */
+int board_wakeup_permitted(void);
+
+#define cpu_is_exynos4()	(s5p_get_cpu_id() == 0xc210)
+#define cpu_is_exynos5()	(s5p_get_cpu_id() == 0xc520)
+
+/**
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int lowlevel_init_subsystems(void);
+
+#endif	/* _EXYNOS_COMMON_CPU_H */
diff --git a/src/cpu/samsung/exynos5-common/exynos5-common.h b/src/cpu/samsung/exynos5-common/exynos5-common.h
new file mode 100644
index 0000000000..5bbc52b736
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/exynos5-common.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Common configuration settings for EXYNOS5 based boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
+
+#ifndef __EXYNOS5_CONFIG_H
+#define __EXYNOS5_CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+#define BUILD_PART_FS_STUFF	1	/* Disk Partition Support */
+
+#define CONFIG_ARCH_CPU_INIT		/* Used to check cpu type */
+
+#include <cpu/samsung/exynos5250/cpu.h>		/* get chip and board defs */
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_CMD_SHA256
+//#define CONFIG_EXYNOS_ACE_SHA
+
+//#define CONFIG_SYS_SDRAM_BASE		0x40000000
+//#define CONFIG_SYS_TEXT_BASE		0x43e00000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI
+//#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* Number of GPIOS to use for board revision detection */
+#define CONFIG_BOARD_REV_GPIO_COUNT	2
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#ifdef CONFIG_SPI_FLASH
+/* Enable SPI H/W Controller Driver support */
+#define CONFIG_EXYNOS_SPI
+
+/* FIXME(dhendrix): We should be concerned with SPI flash parts here... */
+#if 0
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+/* Enable Gigadevice SPI flash support for Snow board */
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+/* Set speed for SPI flash */
+#define CONFIG_SF_DEFAULT_SPEED	50000000
+#endif
+#endif
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE		0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+
+#define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+#define CONFIG_ENV_OFFSET	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE + \
+				 CONFIG_BL2_SIZE)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS	1
+#else /* CONFIG_ENV_IS_IN_MMC */
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+#endif
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+
+/* Set the emmc bus width to 8 */
+#define CONFIG_MSHCI_BUS_WIDTH	8
+#define CONFIG_MSHCI_PERIPH_ID	PERIPH_ID_SDMMC0
+
+#if BUILD_PART_FS_STUFF
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#endif
+
+#if 0
+/* 
+ * FIXME(dhendrix): 0x02050000 was in the u-boot sources, but the docs say the
+ * iRAM range is 0x0202_0000 - 0x0207_7fff (352KB).
+ */
+#define CONFIG_IRAM_TOP		0x02050000
+
+/*
+ * Put the initial stack pointer 1KB below this to allow room for the
+ * SPL marker. This value is arbitrary, but gd_t is placed starting here.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+#endif
+
+/* The place where we put our SPL marker */
+#define CONFIG_SPL_MARKER	(CONFIG_IRAM_TOP - 4)
+
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH	(CONFIG_IRAM_TOP - 0x400)
+#define CONFIG_BOOTSTAGE_STASH_SIZE	0x3fc
+
+/* The top of the SPL stack, also used for early U-Boot init */
+//#define CONFIG_IRAM_STACK	CONFIG_SYS_INIT_SP_ADDR
+
+//#define CONFIG_SPL_LDSCRIPT
+//#define CONFIG_SPL_TEXT_BASE	0x02023400
+//#define CONFIG_SPL_MAX_SIZE	(14 * 1024)
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_THUMB_BUILD
+
+/* We spend about 100us getting from reset to SPL */
+#define CONFIG_SPL_TIME_US	100000
+
+/* Stringify a token */
+#ifndef STRINGIFY
+#define _STRINGIFY(x)	#x
+#define STRINGIFY(x)	_STRINGIFY(x)
+#endif
+
+#endif	/* __EXYNOS5_CONFIG_H */
diff --git a/src/cpu/samsung/exynos5-common/gpio.h b/src/cpu/samsung/exynos5-common/gpio.h
new file mode 100644
index 0000000000..37dd678b09
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/gpio.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_COMMON_GPIO_H
+#define __ASM_ARCH_COMMON_GPIO_H
+
+#ifndef __ASSEMBLY__	/* FIXME: not needed (i hope)? */
+#include <cpu/samsung/s5p-common/gpio.h>
+/* FIXME: s5p's gpio.h and exynos' gpio.h have a lot of conflicting
+   definitions */
+#if 0
+struct s5p_gpio_bank {
+	unsigned int	con;
+	unsigned int	dat;
+	unsigned int	pull;
+	unsigned int	drv;
+	unsigned int	pdn_con;
+	unsigned int	pdn_pull;
+	unsigned char	res1[8];
+};
+
+/* functions */
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+#endif
+
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
+
+#endif
+
+/* Pin configurations */
+#define EXYNOS_GPIO_INPUT	0x0
+#define EXYNOS_GPIO_OUTPUT	0x1
+#define EXYNOS_GPIO_IRQ	0xf
+#define EXYNOS_GPIO_FUNC(x)	(x)
+
+/* Pull mode */
+#define EXYNOS_GPIO_PULL_NONE	0x0
+#define EXYNOS_GPIO_PULL_DOWN	0x1
+#define EXYNOS_GPIO_PULL_UP	0x3
+
+/* Drive Strength level */
+#define EXYNOS_GPIO_DRV_1X	0x0
+#define EXYNOS_GPIO_DRV_3X	0x1
+#define EXYNOS_GPIO_DRV_2X	0x2
+#define EXYNOS_GPIO_DRV_4X	0x3
+#define EXYNOS_GPIO_DRV_FAST	0x0
+#define EXYNOS_GPIO_DRV_SLOW	0x1
+#endif
diff --git a/src/cpu/samsung/exynos5-common/mmc.h b/src/cpu/samsung/exynos5-common/mmc.h
new file mode 100644
index 0000000000..4e435893aa
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/mmc.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_COMMON_MMC_H_
+#define __ASM_ARCH_COMMON_MMC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_mmc {
+	unsigned int	sysad;
+	unsigned short	blksize;
+	unsigned short	blkcnt;
+	unsigned int	argument;
+	unsigned short	trnmod;
+	unsigned short	cmdreg;
+	unsigned int	rspreg0;
+	unsigned int	rspreg1;
+	unsigned int	rspreg2;
+	unsigned int	rspreg3;
+	unsigned int	bdata;
+	unsigned int	prnsts;
+	unsigned char	hostctl;
+	unsigned char	pwrcon;
+	unsigned char	blkgap;
+	unsigned char	wakcon;
+	unsigned short	clkcon;
+	unsigned char	timeoutcon;
+	unsigned char	swrst;
+	unsigned int	norintsts;	/* errintsts */
+	unsigned int	norintstsen;	/* errintstsen */
+	unsigned int	norintsigen;	/* errintsigen */
+	unsigned short	acmd12errsts;
+	unsigned char	res1[2];
+	unsigned int	capareg;
+	unsigned char	res2[4];
+	unsigned int	maxcurr;
+	unsigned char	res3[0x34];
+	unsigned int	control2;
+	unsigned int	control3;
+	unsigned char	res4[4];
+	unsigned int	control4;
+	unsigned char	res5[0x6e];
+	unsigned short	hcver;
+	unsigned char	res6[0xFF00];
+};
+
+struct mmc_host {
+	struct s5p_mmc *reg;
+	unsigned int version;	/* SDHCI spec. version */
+	unsigned int clock;	/* Current clock (MHz) */
+	int dev_index;
+};
+
+#ifdef CONFIG_OF_CONTROL
+int s5p_mmc_init(const void *blob);
+#else
+int s5p_mmc_init(int dev_index, int bus_width);
+#endif
+
+#endif	/* __ASSEMBLY__ */
+#endif
diff --git a/src/cpu/samsung/exynos5-common/mshc.h b/src/cpu/samsung/exynos5-common/mshc.h
new file mode 100644
index 0000000000..bdb0a9c10d
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/mshc.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#ifndef __ASM_ARCH_COMMON_MSHC_H
+#define __ASM_ARCH_COMMON_MSHC_H
+
+#include <asm/arch/pinmux.h>
+#ifndef __ASSEMBLY__
+struct mshci_host {
+	struct s5p_mshci	*reg;		/* Mapped address */
+	unsigned int		clock;		/* Current clock in MHz */
+	enum periph_id	peripheral;
+};
+
+struct s5p_mshci {
+	unsigned int	ctrl;
+	unsigned int	pwren;
+	unsigned int	clkdiv;
+	unsigned int	clksrc;
+	unsigned int	clkena;
+	unsigned int	tmout;
+	unsigned int	ctype;
+	unsigned int	blksiz;
+	unsigned int	bytcnt;
+	unsigned int	intmask;
+	unsigned int	cmdarg;
+	unsigned int	cmd;
+	unsigned int	resp0;
+	unsigned int	resp1;
+	unsigned int	resp2;
+	unsigned int	resp3;
+	unsigned int	mintsts;
+	unsigned int	rintsts;
+	unsigned int	status;
+	unsigned int	fifoth;
+	unsigned int	cdetect;
+	unsigned int	wrtprt;
+	unsigned int	gpio;
+	unsigned int	tcbcnt;
+	unsigned int	tbbcnt;
+	unsigned int	debnce;
+	unsigned int	usrid;
+	unsigned int	verid;
+	unsigned int	hcon;
+	unsigned int	uhs_reg;
+	unsigned int	rst_n;
+	unsigned char	reserved1[4];
+	unsigned int	bmod;
+	unsigned int	pldmnd;
+	unsigned int	dbaddr;
+	unsigned int	idsts;
+	unsigned int	idinten;
+	unsigned int	dscaddr;
+	unsigned int	bufaddr;
+	unsigned int	clksel;
+	unsigned char	reserved2[460];
+	unsigned int	cardthrctl;
+};
+
+/*
+ * Struct idma
+ * Holds the descriptor list
+ */
+struct mshci_idmac {
+	u32	des0;
+	u32	des1;
+	u32	des2;
+	u32	des3;
+};
+
+/*  Control Register  Register */
+#define CTRL_RESET	(0x1 << 0)
+#define FIFO_RESET	(0x1 << 1)
+#define DMA_RESET	(0x1 << 2)
+#define DMA_ENABLE	(0x1 << 5)
+#define SEND_AS_CCSD	(0x1 << 10)
+#define ENABLE_IDMAC    (0x1 << 25)
+
+/*  Power Enable Register */
+#define POWER_ENABLE	(0x1 << 0)
+
+/*  Clock Enable Register */
+#define CLK_ENABLE	(0x1 << 0)
+#define CLK_DISABLE	(0x0 << 0)
+
+/* Timeout Register */
+#define TMOUT_MAX	0xffffffff
+
+/*  Card Type Register */
+#define PORT0_CARD_WIDTH1	0
+#define PORT0_CARD_WIDTH4	(0x1 << 0)
+#define PORT0_CARD_WIDTH8	(0x1 << 16)
+
+/*  Interrupt Mask Register */
+#define INTMSK_ALL	0xffffffff
+#define INTMSK_RE	(0x1 << 1)
+#define INTMSK_CDONE	(0x1 << 2)
+#define INTMSK_DTO	(0x1 << 3)
+#define INTMSK_DCRC	(0x1 << 7)
+#define INTMSK_RTO	(0x1 << 8)
+#define INTMSK_DRTO	(0x1 << 9)
+#define INTMSK_HTO	(0x1 << 10)
+#define INTMSK_FRUN	(0x1 << 11)
+#define INTMSK_HLE	(0x1 << 12)
+#define INTMSK_SBE	(0x1 << 13)
+#define INTMSK_ACD	(0x1 << 14)
+#define INTMSK_EBE	(0x1 << 15)
+
+/* Command Register */
+#define CMD_RESP_EXP_BIT	(0x1 << 6)
+#define CMD_RESP_LENGTH_BIT	(0x1 << 7)
+#define CMD_CHECK_CRC_BIT	(0x1 << 8)
+#define CMD_DATA_EXP_BIT	(0x1 << 9)
+#define CMD_RW_BIT		(0x1 << 10)
+#define CMD_SENT_AUTO_STOP_BIT	(0x1 << 12)
+#define CMD_WAIT_PRV_DAT_BIT	(0x1 << 13)
+#define CMD_SEND_CLK_ONLY	(0x1 << 21)
+#define CMD_USE_HOLD_REG	(0x1 << 29)
+#define CMD_STRT_BIT		(0x1 << 31)
+#define CMD_ONLY_CLK		(CMD_STRT_BIT | CMD_SEND_CLK_ONLY | \
+				CMD_WAIT_PRV_DAT_BIT)
+
+/*  Raw Interrupt Register */
+#define DATA_ERR	(INTMSK_EBE | INTMSK_SBE | INTMSK_HLE |	\
+			INTMSK_FRUN | INTMSK_EBE | INTMSK_DCRC)
+#define DATA_TOUT	(INTMSK_HTO | INTMSK_DRTO)
+
+/*  Status Register */
+#define DATA_BUSY	(0x1 << 9)
+
+/*  FIFO Threshold Watermark Register */
+#define TX_WMARK	(0xFFF << 0)
+#define RX_WMARK	(0xFFF << 16)
+#define MSIZE_MASK	(0x7 << 28)
+
+/* DW DMA Mutiple Transaction Size */
+#define MSIZE_8		(2 << 28)
+
+/*  Bus Mode Register */
+#define BMOD_IDMAC_RESET	(0x1 << 0)
+#define BMOD_IDMAC_FB		(0x1 << 1)
+#define BMOD_IDMAC_ENABLE	(0x1 << 7)
+
+/* IDMAC bits */
+#define MSHCI_IDMAC_OWN		(0x1 << 31)
+#define MSHCI_IDMAC_CH		(0x1 << 4)
+#define MSHCI_IDMAC_FS		(0x1 << 3)
+#define MSHCI_IDMAC_LD		(0x1 << 2)
+
+int s5p_mshci_init(const void *blob);
+
+#endif
+#endif
+
diff --git a/src/cpu/samsung/exynos5-common/pwm.h b/src/cpu/samsung/exynos5-common/pwm.h
new file mode 100644
index 0000000000..e35d88d2d6
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/pwm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_COMMON_PWM_H_
+#define __ASM_ARM_ARCH_COMMON_PWM_H_
+
+#define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
+#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1		0		/* 1/1 period */
+#define MUX_DIV_2		1		/* 1/2 period */
+#define MUX_DIV_4		2		/* 1/4 period */
+#define MUX_DIV_8		3		/* 1/8 period */
+#define MUX_DIV_16		4		/* 1/16 period */
+
+#define MUX_DIV_SHIFT(x)	(x * 4)
+
+#define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
+
+#define TCON_START(x)		(1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD	(1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+	unsigned int	tcfg0;
+	unsigned int	tcfg1;
+	unsigned int	tcon;
+	unsigned int	tcntb0;
+	unsigned int	tcmpb0;
+	unsigned int	tcnto0;
+	unsigned int	tcntb1;
+	unsigned int	tcmpb1;
+	unsigned int	tcnto1;
+	unsigned int	tcntb2;
+	unsigned int	tcmpb2;
+	unsigned int	tcnto2;
+	unsigned int	tcntb3;
+	unsigned int	tcmpb3;
+	unsigned int	tcnto3;
+	unsigned int	tcntb4;
+	unsigned int	tcnto4;
+	unsigned int	tintcstat;
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/src/cpu/samsung/exynos5-common/spi.h b/src/cpu/samsung/exynos5-common/spi.h
new file mode 100644
index 0000000000..3430ac1ab2
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/spi.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+	unsigned int		ch_cfg;		/* 0x00 */
+	unsigned char		reserved0[4];
+	unsigned int		mode_cfg;	/* 0x08 */
+	unsigned int		cs_reg;		/* 0x0c */
+	unsigned char		reserved1[4];
+	unsigned int		spi_sts;	/* 0x14 */
+	unsigned int		tx_data;	/* 0x18 */
+	unsigned int		rx_data;	/* 0x1c */
+	unsigned int		pkt_cnt;	/* 0x20 */
+	unsigned char		reserved2[4];
+	unsigned int		swap_cfg;	/* 0x28 */
+	unsigned int		fb_clk;		/* 0x2c */
+	unsigned char		padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ	50000000
+
+#define SPI_TIMEOUT_MS		10
+
+#define SF_READ_DATA_CMD	0x3
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN		(1 << 6)
+#define SPI_CH_RST		(1 << 5)
+#define SPI_SLAVE_MODE		(1 << 4)
+#define SPI_CH_CPOL_L		(1 << 3)
+#define SPI_CH_CPHA_B		(1 << 2)
+#define SPI_RX_CH_ON		(1 << 1)
+#define SPI_TX_CH_ON		(1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD	(0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD	(0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT	(1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE		(1 << 25)
+#define SPI_FIFO_LVL_MASK	0x1ff
+#define SPI_TX_LVL_OFFSET	6
+#define SPI_RX_LVL_OFFSET	15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS		(0 << 0)
+#define SPI_FB_DELAY_90		(1 << 0)
+#define SPI_FB_DELAY_180	(2 << 0)
+#define SPI_FB_DELAY_270	(3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN	(1 << 16)
+
+/* Swap config */
+#define SPI_TX_SWAP_EN		(1 << 0)
+#define SPI_TX_BYTE_SWAP	(1 << 2)
+#define SPI_TX_HWORD_SWAP	(1 << 3)
+#define SPI_TX_BYTE_SWAP	(1 << 2)
+#define SPI_RX_SWAP_EN		(1 << 4)
+#define SPI_RX_BYTE_SWAP	(1 << 6)
+#define SPI_RX_HWORD_SWAP	(1 << 7)
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/src/cpu/samsung/exynos5-common/spl.h b/src/cpu/samsung/exynos5-common/spl.h
new file mode 100644
index 0000000000..1df4aed424
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/spl.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <cpu/samsung/exynos-common/cpu.h>
+/* FIXME(dhendrix): non-common header included by a common header... */
+#include <cpu/samsung/exynos5250/dmc.h>
+
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+	/* Add fields as and when required */
+	u32		signature;
+	u32		version;	/* Version number */
+	u32		size;		/* Size of block */
+	/**
+	 * Parameters we expect, in order, terminated with \0. Each parameter
+	 * is a single character representing one 32-bit word in this
+	 * structure.
+	 *
+	 * Valid characters in this string are:
+	 *
+	 * Code		Name
+	 * v		mem_iv_size
+	 * m		mem_type
+	 * u		uboot_size
+	 * b		boot_source
+	 * f		frequency_mhz (memory frequency in MHz)
+	 * a		ARM clock frequency in MHz
+	 * s		serial base address
+	 * i		i2c base address for early access (meant for PMIC)
+	 * r		board rev GPIO numbers used to read board revision
+	 *			(lower halfword=bit 0, upper=bit 1)
+	 * M		Memory Manufacturer name
+	 * w		Bad Wake GPIO number
+	 * \0		termination
+	 */
+	char		params[12];	/* Length must be word-aligned */
+	u32		mem_iv_size;	/* Memory channel interleaving size */
+	enum ddr_mode	mem_type;	/* Type of on-board memory */
+	/*
+	 * U-boot size - The iROM mmc copy function used by the SPL takes a
+	 * block count paramter to describe the u-boot size unlike the spi
+	 * boot copy function which just uses the u-boot size directly. Align
+	 * the u-boot size to block size (512 bytes) when populating the SPL
+	 * table only for mmc boot.
+	 */
+	u32		uboot_size;
+	enum boot_mode	boot_source;	/* Boot device */
+	unsigned	frequency_mhz;	/* Frequency of memory in MHz */
+	unsigned	arm_freq_mhz;	/* ARM Frequency in MHz */
+	u32		serial_base;	/* Serial base address */
+	u32		i2c_base;	/* i2c base address */
+	u32		board_rev_gpios;	/* Board revision GPIOs */
+	enum mem_manuf	mem_manuf;	/* Memory Manufacturer */
+	u32		bad_wake_gpio;	/* If high at wake time disallow wake */
+} __attribute__((__packed__));
+
+/**
+ * Validate signature and return a pointer to the parameter table.  If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+/*
+ * Initialize the timer and serial driver in SPL u-boot.
+ * Besides the serial driver, it also setup the minimal set of its dependency,
+ * like gd struct, pinmux, and serial.
+ */
+void spl_early_init(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
diff --git a/src/cpu/samsung/exynos5-common/sromc.h b/src/cpu/samsung/exynos5-common/sromc.h
new file mode 100644
index 0000000000..b413373cf4
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/sromc.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for SROMC
+ *
+ */
+
+#ifndef __ASM_ARCH_COMMON_SROMC_H_
+#define __ASM_ARCH_COMMON_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
+						/* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x)  (x << 8)  /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4)  /* page mode access cycle */
+#define SROMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+	unsigned int	bw;
+	unsigned int	bc[4];
+};
+#endif	/* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+enum {
+	FDT_SROM_PMC,
+	FDT_SROM_TACP,
+	FDT_SROM_TAH,
+	FDT_SROM_TCOH,
+	FDT_SROM_TACC,
+	FDT_SROM_TCOS,
+	FDT_SROM_TACS,
+
+	FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+	u8 bank;	/* srom bank number */
+	u8 width;	/* bus width in bytes */
+	unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
+#endif /* __ASM_ARCH_COMMON_SROMC_H_ */
diff --git a/src/cpu/samsung/exynos5-common/sys_proto.h b/src/cpu/samsung/exynos5-common/sys_proto.h
new file mode 100644
index 0000000000..11f1636eac
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/sys_proto.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h
new file mode 100644
index 0000000000..350e224b86
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/uart.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXYNOS_COMMON_UART_H_
+#define __EXYNOS_COMMON_UART_H_
+
+/* baudrate rest value */
+union br_rest {
+	unsigned short	slot;		/* udivslot */
+	unsigned char	value;		/* ufracval */
+};
+
+struct s5p_uart {
+	unsigned int	ulcon;
+	unsigned int	ucon;
+	unsigned int	ufcon;
+	unsigned int	umcon;
+	unsigned int	utrstat;
+	unsigned int	uerstat;
+	unsigned int	ufstat;
+	unsigned int	umstat;
+	unsigned char	utxh;
+	unsigned char	res1[3];
+	unsigned char	urxh;
+	unsigned char	res2[3];
+	unsigned int	ubrdiv;
+	union br_rest	rest;
+	unsigned char	res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+	return 0;
+}
+
+#endif
diff --git a/src/cpu/samsung/exynos5-common/watchdog.h b/src/cpu/samsung/exynos5-common/watchdog.h
new file mode 100644
index 0000000000..af986388a3
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/watchdog.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_COMMON_WATCHDOG_H_
+#define __ASM_ARM_ARCH_COMMON_WATCHDOG_H_
+
+#define WTCON_RESET_OFFSET	0
+#define WTCON_INTEN_OFFSET	2
+#define WTCON_CLKSEL_OFFSET	3
+#define WTCON_EN_OFFSET		5
+#define WTCON_PRE_OFFSET	8
+
+#define WTCON_CLK_16		0x0
+#define WTCON_CLK_32		0x1
+#define WTCON_CLK_64		0x2
+#define WTCON_CLK_128		0x3
+
+#define WTCON_CLK(x)		((x & 0x3) << WTCON_CLKSEL_OFFSET)
+#define WTCON_PRESCALER(x)	((x) << WTCON_PRE_OFFSET)
+#define WTCON_EN		(0x1 << WTCON_EN_OFFSET)
+#define WTCON_RESET		(0x1 << WTCON_RESET_OFFSET)
+#define WTCON_INT		(0x1 << WTCON_INTEN_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct s5p_watchdog {
+	unsigned int wtcon;
+	unsigned int wtdat;
+	unsigned int wtcnt;
+	unsigned int wtclrint;
+};
+
+/* functions */
+void wdt_stop(void);
+void wdt_start(unsigned int timeout);
+#endif	/* __ASSEMBLY__ */
+
+#endif