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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-06-28 10:08:51 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-04 06:53:12 +0000 |
| commit | 6e2d0c1b90251b4b61af582d2598cdbd38591db7 (patch) | |
| tree | 05dd94e809ddb67fbb5b1c6f1d1c6a2ad5736a68 /src/cpu | |
| parent | 8f23b5d4343c5c8ec1f7f7d453f9d8784fc0d5a2 (diff) | |
arch/x86: Adjust size of postcar stack
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3cbdf44c1d..47b9976786 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,8 +38,6 @@ #include <cpu/intel/romstage.h> #include "haswell.h" -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -48,7 +46,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |