diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-09 22:07:29 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-10 10:23:22 +0000 |
| commit | 49be1a93467e6bd1bd61ec7889c0a6f24e824288 (patch) | |
| tree | 51d326d830754a3a6c0003914012d9811d156bd7 /src/cpu | |
| parent | ecdc714ef8eeb672c1125ce810aaf76d0752f520 (diff) | |
Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
This reverts commit ceaf959678905f44a54a116f37bd15acab5d4608.
The AMD Picasso SoC doesn't support x2APIC and neither advertises the
presence of its support via bit 21 in EAX of CPUID leaf 1 nor has the
bit 10 in the APIC base address MSR 0x1b set, but it does have 0xd CPUID
leaves, so just checking for the presence of that CPUID leaf isn't
sufficient to be sure that EDX of the CPUID leaf 0xb will contain a
valid APIC ID.
In the case of Picasso EDX of the CPUID leaf 0xb returns 0 for all cores
which causes coreboot to get stuck somewhere at the end of MP init.
I'm not 100% sure if we should additionally check bit 21 in EAX of CPUID
function 1 is set instead of adding back the is_x2apic_mode check.
TEST=Mandolin with a Picasso SoC boots again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1e3c55ce2d048b14c08e06bb79810179a87993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/smm/smm_stub.S | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 25a35aabbe..c83839cc01 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -101,25 +101,30 @@ smm_trampoline32: * the OS can manipulate the APIC id use the non-changing cpuid result * for APIC id (eax). A table is used to handle a discontiguous * APIC id space. */ +apic_id: + mov $LAPIC_BASE_MSR, %ecx + rdmsr + and $LAPIC_BASE_X2APIC_ENABLED, %eax + cmp $LAPIC_BASE_X2APIC_ENABLED, %eax + jne xapic - mov $0, %eax - cpuid - cmp $0xb, %eax - jc 1f +x2apic: mov $0xb, %eax mov $0, %ecx cpuid mov %edx, %eax - jmp 2f -1: + jmp apicid_end + +xapic: mov $1, %eax cpuid mov %ebx, %eax shr $24, %eax -2: +apicid_end: mov $(apic_to_cpu_num), %ebx xor %ecx, %ecx + 1: cmp (%ebx, %ecx, 2), %ax je 1f |