diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-02-07 00:51:18 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-18 20:50:15 +0100 |
| commit | 2ad1dbaf2a2dfe373ff89927202acc01e36c7cd4 (patch) | |
| tree | a29fe94cc9daf897d563c61bc5b99325e91adf4c /src/cpu | |
| parent | 38d9423dbe300514e1ba7224a962650980a96217 (diff) | |
haswell: move call site of save_mrc_data()
The save_mrc_data() was previously called conditionally
in the raminit code. The save_mrc_data() function was called
in the non-S3 wake paths. However, the common romstage_common()
code was checking cbmem initialization things on s3 wake. Between
the two callers cbmem_initialize() was being called twice in the
non-s3 wake paths. Moreover, saving of the mrc data was not allowed
when CONFIG_EARLY_CBMEM_INIT wasn't enabled.
Therefore, move the save_mrc_data() to romstage_common. It already has
the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT
requirement from save_mrc_data() as well as the call to cbmem_initialize().
Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2756
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b0e2cc6c9..3ce04e274b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -230,6 +230,10 @@ void romstage_common(const struct romstage_params *params) - HIGH_MEMORY_SIZE)); #endif + /* Save data returned from MRC on non-S3 resumes. */ + if (boot_mode != 2) + save_mrc_data(params->pei_data); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. |