intel/smm: Provide common smm_relocation_params

Pull in all copies of smm_relocation_params structs defined
for intel platforms.

Pull in all the inlined MSR accessors to the header file.

Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 23 insertions, 62 deletions

diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
index 4fa3affb55..0f2a65238c 100644
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@@ -26,3 +26,7 @@ config CPU_INTEL_COMMON_HYPERTHREADING
 	bool
 
 endif
+
+config CPU_INTEL_COMMON_SMM
+	bool
+	default y if CPU_INTEL_COMMON
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index c33a00a95c..8419746cdc 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -45,49 +45,7 @@
 #define SMRR_SUPPORTED (1 << 11)
 #define PRMRR_SUPPORTED (1 << 12)
 
-struct smm_relocation_params {
-	uintptr_t ied_base;
-	size_t ied_size;
-	msr_t smrr_base;
-	msr_t smrr_mask;
-	msr_t prmrr_base;
-	msr_t prmrr_mask;
-	msr_t uncore_prmrr_base;
-	msr_t uncore_prmrr_mask;
-	/* The smm_save_state_in_msrs field indicates if SMM save state
-	 * locations live in MSRs. This indicates to the CPUs how to adjust
-	 * the SMMBASE and IEDBASE */
-	int smm_save_state_in_msrs;
-};
-
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
 
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
-	wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
-	wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG,
-	       "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->uncore_prmrr_base.lo,
-	       relo_params->uncore_prmrr_mask.lo);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
 
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc
new file mode 100644
index 0000000000..a49b796caf
--- /dev/null
+++ b/src/cpu/intel/smm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 5350d1c930..c177e9b952 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -39,17 +39,6 @@
 #define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
 
-
-struct smm_relocation_params {
-	uintptr_t ied_base;
-	size_t ied_size;
-	msr_t smrr_base;
-	msr_t smrr_mask;
-};
-
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
 /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
    differently. The MSR are at different location from the rest
    and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
@@ -88,15 +77,6 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
 	wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
 }
 
-static void write_smrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-
-	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
 	uintptr_t tseg_base;
diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c
new file mode 100644
index 0000000000..860c095abf
--- /dev/null
+++ b/src/cpu/intel/smm/smm_reloc.c
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/smm_reloc.h>
+
+struct smm_relocation_params smm_reloc_params;
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index 9c18d44945..55d1fad7cb 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -6,6 +6,8 @@ ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
 ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c
 ramstage-y += backup_default_smm.c
 
+subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
+
 additional-dirs += $(obj)/cpu/x86
 
 SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf