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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-07-23 19:00:52 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-08-30 22:06:39 +0000 |
| commit | d10a10befd7046e50c72903ac8799e81d5f52a20 (patch) | |
| tree | 5fd825996b711c0c2d6d8d3101be573ba03704ae /src/cpu | |
| parent | f0b6b30c46049e9849474965c87c83e7540e25dc (diff) | |
mb/google/volteer: Update flashmap descriptor for CSE Lite FW update
To support CSE Lite firmware update, CSE RW partition is extracted from
CSE blob binary and added to FW_MAIN_A and FW_MAIN_B.
CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and
FW_MAIN_B is increased to avoid an overflow.
BUG=b:140448618
TEST=build with me_rw binary blob for volteer and boot to kernel.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions