diff options
| author | Julius Werner <jwerner@chromium.org> | 2013-09-18 14:39:50 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-08-10 22:18:50 +0200 |
| commit | 985ff36bee24d1e5a8bd698409a0a05e15528c01 (patch) | |
| tree | 029ed9a091d2c79b345e159765c153bf4000646e /src/cpu | |
| parent | 802ad521804b8a9f473780fdff4058dd3f8520c3 (diff) | |
armv7: Support stack dump after exceptions
This patch enhances the armv7 exception handlers in Coreboot and
libpayload to show the correct SP and LR registers from the aborted
context, and also dump a part of the current stack. Since we cannot
access the banked registers of SVC mode from a different exception mode,
it changes Coreboot (and its payloads) to run in System mode instead. As
both modes can execute all privileged instructions, this should not have
any noticeable effect on firmware operation (please correct me if I'm
wrong!).
Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170045
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6538
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/samsung/exynos5420/smp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/samsung/exynos5420/smp.c b/src/cpu/samsung/exynos5420/smp.c index 2a0656bcaf..069110c069 100644 --- a/src/cpu/samsung/exynos5420/smp.c +++ b/src/cpu/samsung/exynos5420/smp.c @@ -169,7 +169,7 @@ static void core_start_execution(void) struct exynos5_power *power = samsung_get_base_power(); enable_smp(); - set_svc32_mode(); + set_system_mode(); cpu_id = read_mpidr() & 0x3; /* up to 4 processors for one cluster. */ cpu_state = exynos_cpu_states->cpu_states[cpu_id]; @@ -221,7 +221,7 @@ static void low_power_start(void) sev(); } - set_svc32_mode(); + set_system_mode(); /* Whenever a Cortex A-15 core powers on, iROM resets its L2 cache * so we need to configure again. */ |