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authorIndrek Kruusa <indrek.kruusa@artecdesign.ee>2006-08-03 16:48:18 +0000
committerStefan Reinauer <stepan@openbios.org>2006-08-03 16:48:18 +0000
commit8e3464109e47945b1a4d7e3dd0c6e291593de70a (patch)
tree03493e297dc332c8c7613303eb874e12830e0a5a /src/cpu
parent8ad7c06535694959952b7d64a9649cb9534abd2a (diff)
Changelog:
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_lx/model_lx_init.c28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
index ac075eca59..9eee1833e9 100644
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ b/src/cpu/amd/model_lx/model_lx_init.c
@@ -5,7 +5,6 @@
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
-#include <cpu/amd/lxdef.h>
static void vsm_end_post_smi(void)
{
@@ -19,37 +18,10 @@ static void vsm_end_post_smi(void)
static void model_lx_init(device_t dev)
{
-
- msr_t msr;
-
printk_debug("model_lx_init\n");
/* Turn on caching if we haven't already */
- /* Instruction Memory Configuration register
- * set EBE bit, required when L2 cache is enabled
- */
- msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= 0x400;
- wrmsr(CPU_IM_CONFIG, msr);
-
- /* Data Memory Subsystem Configuration register
- * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
- */
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= 0x4000;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- /* invalidate L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x10;
- wrmsr(L2_CONFIG_MSR, msr);
-
- /* Enable L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x0f;
- wrmsr(L2_CONFIG_MSR, msr);
-
x86_enable_cache();
/* Enable the local cpu apics */