AMD boards (non-AGESA): Cleanup earlymtrr.c includes

Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4523
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

5 files changed, 8 insertions, 9 deletions

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 3fe496e44c..3b3738c99a 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -4,9 +4,9 @@
 #include <string.h>
 #include <arch/stages.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include "cbmem.h"
 #include "cpu/amd/car/disable_cache_as_ram.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index c78f6403d8..c82a26e135 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -1,3 +1,4 @@
+romstage-y += ../../x86/mtrr/earlymtrr.c
 ramstage-y += model_10xxx_init.c
 ramstage-y += processor_name.c
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 3ebd7f2358..ed009d72a4 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -25,7 +25,6 @@
 #include <northbridge/amd/amdht/AsPsDefs.h>
 #include <northbridge/amd/amdht/porting.h>
 
-#include <cpu/x86/mtrr/earlymtrr.c>
 #include <northbridge/amd/amdfam10/raminit_amdmct.c>
 #include <reset.h>
 
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index e016235f7e..eb62640656 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -1,3 +1,5 @@
+romstage-y += ../../x86/mtrr/earlymtrr.c
+
 # no conditionals here. If you include this file from a socket, then you get all the binaries.
 ramstage-y += model_fxx_init.c
 ramstage-y += model_fxx_update_microcode.c
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index f16da279c6..36f94cdf05 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -1,13 +1,12 @@
-#ifndef EARLYMTRR_C
-#define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
 
-static void set_var_mtrr(
+#ifdef __ROMCC__
+static
+#endif
+void set_var_mtrr(
 	unsigned reg, unsigned base, unsigned size, unsigned type)
-
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
 	/* FIXME: It only support 4G less range */
@@ -104,5 +103,3 @@ static inline int early_mtrr_init_detected(void)
 	return msr.lo & MTRRdefTypeEn;
 }
 #endif
-
-#endif /* EARLYMTRR_C */