diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-01 23:58:59 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-10 20:00:56 +0100 |
| commit | 1f780994ebb7b89cf9e47e7bb9533395b8f4dad0 (patch) | |
| tree | 14c5a82c2462eca0513255da5eed93edc1bc7616 /src/cpu | |
| parent | 453b54371681f8810ed50b41efbd7e09dc0f63d6 (diff) | |
cpu/amd/car: Add romstage BSP stack overrun detection
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable. There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.
Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 6 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 8 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 9874ec47a2..3295ccc3b1 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -20,7 +20,7 @@ #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#define CacheBase CONFIG_DCACHE_RAM_BASE #define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE #define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH @@ -496,6 +496,10 @@ CAR_skip_k8_errata_part2: movl $(CacheBase + CacheSize), %eax movl %eax, %esp + /* Poison the lower stack boundary */ + movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax + movl $0xdeadbeef, (%eax) + post_code(0xa3) jmp CAR_FAM10_ap_out diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 49b9ee3fe3..26e611c8a8 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -98,6 +98,14 @@ void post_cache_as_ram(void) void *resume_backup_memory = NULL; uint32_t family = amd_fam1x_cpu_family(); + /* Verify that the BSP didn't overrun the lower stack + * boundary during romstage execution + */ + volatile uint32_t *lower_stack_boundary; + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) + printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); + struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); if (handoff != NULL) |