diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-03 20:03:18 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-07 12:09:15 +0200 |
| commit | e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch) | |
| tree | f6a10fc93dddada7e49108a5ad06e71590f2d54c /src/cpu | |
| parent | e81ce0483db982c741eebdda649111eee22a853b (diff) | |
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/fidvid.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/quadcore/quadcore_id.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 3f0eca5f95..156333f12c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -45,7 +45,7 @@ * xmm2: Fam10h comparison value * xmm3: Fam15h comparison value * xmm4: Backup EBX - * xmm5: Coreboot init detect + * xmm5: coreboot init detect */ /* Save the BIST result. */ diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 8fe708cbd7..126271875b 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -60,7 +60,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required if the warm reset is issued by coreboot to update NbFid. So it is required or not ? How can I tell who issued warm reset ? - Coreboot transitions to P0 instead, which is not recommended, and does + coreboot transitions to P0 instead, which is not recommended, and does not follow 2.4.2.15.2 to do so. 9.- TODO Requires information on current delivery capability diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index cd83906f0e..9892c12347 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -105,7 +105,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) } } if (fam15h && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. + /* coreboot expects each separate processor die to be on a different nodeid. * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... */ uint32_t f5x84; @@ -123,7 +123,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) id.coreid = id.coreid - core_count; } } else if (rev_gte_d && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. + /* coreboot expects each separate processor die to be on a different nodeid. * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... */ uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1; |