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author | Marc Jones <marc.jones@se-eng.com> | 2012-11-05 17:25:52 -0700 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-27 03:03:05 +0100 |
commit | da3087f67d516350249779745927861c4da2173d (patch) | |
tree | 45020c6ef8b79ae8320fd1ca1452a171861b5e26 /src/cpu | |
parent | db4f875a412e6c41f48a86a79b72465f6cd81635 (diff) |
Mainboard SMI S state handler was using the wrong defines
The PCH register bit definition for sleep type is a little confusing.
For example, 7 is S5. To make this simpler for the mainbaord developer,
the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2).
A couple mainboard SMI handlers were using the PCH define for slp_ty,
so S3 code would be run for S5 and S5 code would never be run.
Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2514
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions