diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-08-30 17:53:13 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-30 17:53:13 +0000 |
| commit | 704b59662d8bf17cac387109a186cc6f702f27f9 (patch) | |
| tree | 12de99d00ac98616d0d4df8b089603649a93b699 /src/cpu | |
| parent | 849498d4471003ff959e0151828abfe9a7be4621 (diff) | |
We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_gx2/syspreinit.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_lx/syspreinit.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/socket_FC_PGA370/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 1b72f6e5aa..1031db0bb6 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,7 +3,7 @@ source src/cpu/intel/Kconfig source src/cpu/via/Kconfig source src/cpu/x86/Kconfig -config USE_DCACHE_RAM +config CACHE_AS_RAM bool default !ROMCC diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 6c66ebaf13..3789fdebdf 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -1,6 +1,6 @@ config CPU_AMD_MODEL_10XXX bool - select USE_DCACHE_RAM + select CACHE_AS_RAM select SSE select SSE2 diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 4f59b6d08a..21fc1ab377 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -1,6 +1,6 @@ config CPU_AMD_MODEL_FXX bool - select USE_DCACHE_RAM + select CACHE_AS_RAM select MMX select SSE select SSE2 diff --git a/src/cpu/amd/model_gx2/syspreinit.c b/src/cpu/amd/model_gx2/syspreinit.c index 5801f33a47..286e6b9fce 100644 --- a/src/cpu/amd/model_gx2/syspreinit.c +++ b/src/cpu/amd/model_gx2/syspreinit.c @@ -16,7 +16,7 @@ static void StartTimer1(void) void SystemPreInit(void) { /* they want a jump ... */ -#ifndef CONFIG_USE_DCACHE_RAM +#ifndef CONFIG_CACHE_AS_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c index 33c6ece942..0d80cba69d 100644 --- a/src/cpu/amd/model_lx/syspreinit.c +++ b/src/cpu/amd/model_lx/syspreinit.c @@ -39,7 +39,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#ifndef CONFIG_USE_DCACHE_RAM +#ifndef CONFIG_CACHE_AS_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig index 7116f32e0a..f3987783a8 100644 --- a/src/cpu/intel/socket_FC_PGA370/Kconfig +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -23,7 +23,7 @@ config CPU_INTEL_SOCKET_FC_PGA370 select CPU_INTEL_MODEL_68X select MMX select SSE - select USE_DCACHE_RAM + select CACHE_AS_RAM select TINY_BOOTBLOCK config DCACHE_RAM_BASE diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 72c471e180..5c83554cb2 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -62,7 +62,7 @@ static inline void cache_lbmem(int type) enable_cache(); } -#if !defined(CONFIG_USE_DCACHE_RAM) || (CONFIG_USE_DCACHE_RAM == 0) +#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ |