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authorElyes HAOUAS <ehaouas@noos.fr>2018-11-26 22:53:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:45 +0000
commit6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch)
treea95ac78c1e4e222971ee9749e9e114494681e9c4 /src/cpu
parent1a5ce95815210032783d01e830390ee5b6a54dc5 (diff)
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/allwinner/a10/clock.c6
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index ae50e06025..8f64f06bc0 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -247,9 +247,9 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
* will always be in spec, as long as AHB is in spec, although the max
* AHB0 clock we can get is 125 MHz
*/
- axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */
- ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */
- apb0 = 2; /* Max 150 MHz */
+ axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */
+ ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */
+ apb0 = 2; /* Max 150 MHz */
ahb_exp = log2_ceil(ahb);
ahb = 1 << ahb_exp;
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 04f709fde8..a589cdb8dd 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -83,7 +83,7 @@ static unsigned long calibrate_tsc_with_pit(void)
if (end.lo <= CALIBRATE_DIVISOR)
goto bad_ctc;
- return CEIL_DIV(end.lo, CALIBRATE_DIVISOR);
+ return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR);
}
/*