diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2017-12-26 17:54:45 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-01-11 02:02:14 +0000 |
commit | 276c06a2f5af4846ecbf21a813f46fac515f4316 (patch) | |
tree | f8733bb6a6dcca02f40778da39e70e69561fb08c /src/cpu | |
parent | 90137e31068a576d6e4cf41aa100ace57a61c1b2 (diff) |
intel/fsp2_0: Issue hard reset in S3 resume for invalid mrc cache data
In S3 resume, for cases if valid mrc cache data is not found or
RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer
would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION.
This gets memory to be retrained in S3 flow. Data context including
that of imdr root pointer would be lost, invoking a hard reset in
romstage post memory init. Issuing hard reset before memory init,
saves fsp memory initialization and training overhead.
BUG=b:70973961
BRANCH=None
TEST=Verify S3 resume flows on soraka.
Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions