diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-29 01:06:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-15 22:55:54 +0000 |
| commit | f6846efd846b65a4295b45b177bd67017f0987f9 (patch) | |
| tree | 7cb2de6c3ad8daffddddebdf62a3b58103d9cb85 /src/cpu | |
| parent | babffce0eb9922e0ab4e07b7e664d85d1c4e6f1c (diff) | |
gm45 boards: Factor out MAX_CPUS
The gm45 northbridge supports at most 4 threads. However, the only two
mobile Core 2 Quad models are not BGA956, so account for that as well.
Change-Id: Ie198ac4c366ec0bd53ddb337b6f9c03c331c73f5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/intel/socket_p/Kconfig | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index eef81d570a..638653c162 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -18,4 +18,8 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config MAX_CPUS + int + default 2 + endif diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 6ba74eea90..a7c8ab1bb8 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -19,4 +19,8 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config MAX_CPUS + int + default 4 + endif |