diff options
| author | David Guckian <david.guckian@intel.com> | 2015-11-14 16:01:33 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:41:00 +0100 |
| commit | d35c264b71c923387f93886ec9507bd052b8bedf (patch) | |
| tree | 95346936980c5cd4c2842b7581bb1ea37df26d4a /src/cpu | |
| parent | 5f06d53bdb3621ff9e232d4f070f9ff4bbacfa4c (diff) | |
intel/fsp_model_406dx: Load APs microcode in model_406dx_init
Load microcode to APs when performing model_406dx_init. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.
Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e
Signed-off-by: David Guckian <david.guckian@intel.com>
Reviewed-on: http://review.coreboot.org/12436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 1c37cc3616..30e7e592bc 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select UDELAY_LAPIC - select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index b25c9979e9..5482e74b7a 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include "model_406dx.h" @@ -168,6 +169,9 @@ static void model_406dx_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); + /* Load microcode */ + intel_update_microcode_from_cbfs(); + /* Clear out pending MCEs */ configure_mca(); |