diff options
| author | Matthias Gazzari <mail@qtux.eu> | 2018-04-29 21:07:58 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-05-01 16:23:56 +0000 |
| commit | cc1e3b64ed3621b06f853166bc767cc2625651d4 (patch) | |
| tree | 41b9bd7afab19f3d3e3636e049aff44b633d57e5 /src/cpu | |
| parent | 15f232df089a6620f7fe2541caa7713422885c72 (diff) | |
Fix freeze during chipset lockdown on Nehalem
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)
and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR
register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue
which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a.
More detailed, either setting the LSB of the 32 bit register at 0x98
of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or
setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the
intel_model_2065x_finalize_smm function) indepentenly causes a freeze
during bootup or a complete session loss on resuming from S3 as described
here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html
It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.
Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile
Processor Series, Datasheet Volume Two" indicates that registers of the
PCI device 00:00.0 cannot be locked manually. Instead, they can only be
locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.
Finally, the addresses and sizes of these registers were partially wrong.
Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT
support compared to the Core i5 and Core i7 processors of a X201).
Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25914
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_2065x/finalize.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x.h | 1 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 50e00bf74a..5e7b3d847c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -54,7 +54,4 @@ void intel_model_2065x_finalize_smm(void) /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); - - /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8bb3b877e8..f87ba77460 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -39,7 +39,6 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e |