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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-05-31 14:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-10-18 04:50:43 +0000
commitb31b033ccc50a2f5c609f5fd2cbfda588994b518 (patch)
tree98ea1170df4ebef18409b92bec5f48a8308d9258 /src/cpu
parent253c356c2bca2a9552a42ea4dd38c71a639877a4 (diff)
cpu/x86/lapic: Drop xapic_write_atomic()
Remove code, which was only needed for B and C2 stepping of P54C. The linux kernel source has commentary on X86_BUG_11AP: * See if we have a good local APIC by checking for buggy Pentia, * i.e. all B steppings and the C2 stepping of P54C when using their * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update") Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index e141ad8ec9..bc0f44fd90 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -128,7 +128,7 @@ static int lapic_start_cpu(unsigned long apicid)
printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk(BIOS_ERR, "Try to reset ESR\n");
- xapic_write_atomic(LAPIC_ESR, 0);
+ lapic_write(LAPIC_ESR, 0);
printk(BIOS_ERR, "ESR is 0x%x\n",
lapic_read(LAPIC_ESR));
}