diff options
author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-16 23:24:26 -0600 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-18 01:26:51 +0100 |
commit | a2f79d5971d3d29c9a3ef006e4ca9b852a3b864f (patch) | |
tree | e4393a2b2dec1db340c381f0f4f4f4a297ac372c /src/cpu | |
parent | 7711c0d5c1170d856c87d9963a790457b55403db (diff) |
cpu/amd/model_10xxx: Add monotonic timer support
Change-Id: Idf37d51c6b53ae85dc96fb609531ceda06ec948c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8470
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 1 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/Makefile.inc | 1 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/monotonic_timer.c | 98 |
3 files changed, 100 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 1b79eb08d9..cd69caecf3 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -9,6 +9,7 @@ config CPU_AMD_MODEL_10XXX select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index f5cf37514c..ba12dcd3ef 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c romstage-y += update_microcode.c +ramstage-y += monotonic_timer.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/amd/model_10xxx/monotonic_timer.c b/src/cpu/amd/model_10xxx/monotonic_timer.c new file mode 100644 index 0000000000..ae29eb97f5 --- /dev/null +++ b/src/cpu/amd/model_10xxx/monotonic_timer.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <timer.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <northbridge/amd/amdht/AsPsDefs.h> +#include <cpu/amd/model_10xxx_msr.h> + +static struct monotonic_counter { + int initialized; + uint32_t core_frequency; + struct mono_time time; + uint64_t last_value; +} mono_counter; + +static inline uint64_t read_counter_msr(void) +{ + msr_t counter_msr; + + counter_msr = rdmsr(TSC_MSR); + + return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo; +} + +static void init_timer(void) +{ + uint8_t model; + uint32_t cpuid_fms; + uint8_t cpufid; + uint8_t cpudid; + uint8_t boost_capable = 0; + + /* Get CPU model */ + cpuid_fms = cpuid_eax(0x80000001); + model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4); + + /* Get boost capability */ + if ((model == 0x8) || (model == 0x9)) { /* revision D */ + boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2; + } + + /* Set up TSC (BKDG v3.62 section 2.9.4)*/ + msr_t msr = rdmsr(HWCR_MSR); + msr.lo |= 0x1000000; + wrmsr(HWCR_MSR, msr); + + /* Get core Pstate 0 frequency in MHz */ + msr = rdmsr(0xC0010064 + boost_capable); + cpufid = (msr.lo & 0x3f); + cpudid = (msr.lo & 0x1c0) >> 6; + mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid); + + mono_counter.last_value = read_counter_msr(); + mono_counter.initialized = 1; +} + +void timer_monotonic_get(struct mono_time *mt) +{ + uint64_t current_tick; + uint32_t usecs_elapsed = 0; + + if (!mono_counter.initialized) + init_timer(); + + current_tick = read_counter_msr(); + if (mono_counter.core_frequency != 0) + usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +} |