diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 11:39:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:22:12 +0000 |
| commit | 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 (patch) | |
| tree | 4d23f557990d8edb3edb1b09e2be3cd609b6acd7 /src/cpu | |
| parent | 6f573217a0920b18ea9febd9c6696a01b0f7c082 (diff) | |
cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_1067x/chip.h | 7 | ||||
| -rw-r--r-- | src/cpu/intel/model_1067x/model_1067x_init.c | 18 |
2 files changed, 3 insertions, 22 deletions
diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h deleted file mode 100644 index b298615e8a..0000000000 --- a/src/cpu/intel/model_1067x/chip.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -struct cpu_intel_model_1067x_config { - int c5 : 1; - int c6 : 1; - int slfm : 1; -}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 02e6032265..825a2468f9 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -9,25 +9,18 @@ #include <cpu/x86/name.h> #include <cpu/intel/smm_reloc.h> -#include "chip.h" - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - const struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - /* Is C5 requested and supported? */ - const int c5 = conf && conf->c5 && + const int c5 = southbridge_support_c5() && (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); /* Is C6 requested and supported? */ - const int c6 = conf && conf->c6 && + const int c6 = southbridge_support_c6() && ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ @@ -75,14 +68,9 @@ static void configure_p_states(const char stepping, const char cores) { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - msr = rdmsr(MSR_EXTENDED_CONFIG); /* Super LFM supported? */ - if (conf && conf->slfm && (msr.lo & (1 << 27))) + if (northbridge_support_slfm() && (msr.lo & (1 << 27))) msr.lo |= (1 << 28); /* Enable Super LFM. */ wrmsr(MSR_EXTENDED_CONFIG, msr); |