diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2004-03-26 18:34:48 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-03-26 18:34:48 +0000 |
| commit | 8cb91dc9f832cb3df7aa74b4990a297d48133cfb (patch) | |
| tree | 3803e1913525e393721a35fe246c40c2a55be0b0 /src/cpu | |
| parent | 23e2e18960d5ffed4bc8bb082f1ef8e471307657 (diff) | |
speed up ecc clear by enable MTRR/Cache first.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/k8/cpufixup.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/k8/cpufixup.c b/src/cpu/k8/cpufixup.c index c25a473d2e..6edfe73bf6 100644 --- a/src/cpu/k8/cpufixup.c +++ b/src/cpu/k8/cpufixup.c @@ -134,10 +134,11 @@ static void set_init_ecc_mtrrs(void) { msr_t msr; int i; + disable_cache(); /* First clear all of the msrs to be safe */ - for(i = 0; i < MTRR_COUNT; i++) { + for (i = 0; i < MTRR_COUNT; i++) { msr_t zero; zero.lo = zero.hi = 0; wrmsr(MTRRphysBase_MSR(i), zero); @@ -165,7 +166,6 @@ static void set_init_ecc_mtrrs(void) enable_cache(); } - static void init_ecc_memory(void) { unsigned long startk, begink, endk; |