diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-17 06:45:56 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-02 04:57:07 +0000 |
| commit | 6e37b0acb6b760352fe3aa5905a6234ac7969e5b (patch) | |
| tree | 598358924025a89e258813b6fb2817f0b9f08114 /src/cpu | |
| parent | c43cd97802dece98fb9cc0de05b1c54762b3f57d (diff) | |
binaryPI: Enable EARLY_CBMEM_INIT
Also moves postcar stack to CBMEM.
Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/pi/romstage.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index 393cbd4aeb..9a5fbac003 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -14,10 +14,12 @@ */ #include <arch/cpu.h> +#include <cbmem.h> #include <cpu/amd/car.h> #include <cpu/x86/mtrr.h> #include <console/console.h> #include <program_loading.h> +#include <romstage_handoff.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> @@ -28,12 +30,20 @@ void asmlinkage early_all_cores(void) void * asmlinkage romstage_main(unsigned long bist) { - uintptr_t stack_top = CACHE_TMP_RAMTOP; + int s3resume = 0; u8 initial_apic_id = cpuid_ebx(1) >> 24; /* Only BSP returns from here. */ cache_as_ram_main(bist, initial_apic_id); + cbmem_recovery(s3resume); + + romstage_handoff_init(s3resume); + + uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += HIGH_ROMSTAGE_STACK_SIZE; + printk(BIOS_DEBUG, "Move CAR stack.\n"); return (void*)stack_top; } |