diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-03-02 14:21:32 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-04 10:39:39 +0000 |
| commit | 573481bf6f74af7e84fda2db63a8c6aa2466f746 (patch) | |
| tree | 937a39290ed8b31a9c3ecf2311dd6a9758bca400 /src/cpu | |
| parent | 63266c7e6697a3ccbe2ec370e89605c8d7ec7e33 (diff) | |
cpu/intel/model_206ax: Lock MSR on all cores
Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one
handling APM_CNT_FINALIZE.
Tested on HP Z220: FWTS no longer reports this as an issue.
Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index d51fb21847..a7754ae969 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -25,9 +25,6 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); - /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2571f8cb40..773940850d 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -256,6 +256,8 @@ static void configure_c_states(void) msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection msr.lo |= 7; // No package C-state limit + + msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); |