x86: Drop -Wa,--divide

Fix up all the code that is using / to use >> for divisions instead.

Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10819
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

9 files changed, 21 insertions, 21 deletions

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index ac6ea33b98..133daace3d 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -240,15 +240,15 @@ clear_fixed_var_mtrr_out:
  * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
 	extractmask gas_bug_workaround, %eax
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
 	extractmask gas_bug_workaround, %edx
 	/*
 	 * Without the gas bug workaround, the entire macro would consist
 	 * only of the two lines below:
-	 *   extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	 *   extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+	 *   extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
+	 *   extractmask (((\carsize - \windowoffset) >> 12)), %edx
 	 */
 .endm
 
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 7ddd3af803..837352f8a7 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -166,7 +166,7 @@ done_cache_as_ram_main:
 	/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
 
 	push   %edi
-	mov    $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
+	mov    $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
 	push   %esi
 	mov    $(CONFIG_DCACHE_RAM_BASE),%edi
 	mov    %edi,%esi
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index df6f942f58..bcb0d4b52a 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -192,7 +192,7 @@ done_cache_as_ram_main:
 	 * copying it back to itself to invalidate the cache */
 
 	push   %edi
-	mov    $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
+	mov    $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
 	push   %esi
 	mov    $(CONFIG_DCACHE_RAM_BASE),%edi
 	mov    %edi,%esi
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 1d8ea8d844..f9be6e890f 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out:
  * windowoffset is the 32k-aligned window into CAR size.
  */
 .macro simplemask carsize, windowoffset
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+	.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
 	extractmask gas_bug_workaround, %eax
-	.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+	.set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
 	extractmask gas_bug_workaround, %edx
 	/*
 	 * Without the gas bug workaround, the entire macro would consist
 	 * only of the two lines below:
-	 *   extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
-	 *   extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+	 *   extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
+	 *   extractmask (((\carsize - \windowoffset) >> 12)), %edx
 	 */
 .endm
 
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 29d7113600..193ad418c0 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -47,7 +47,7 @@ cache_as_ram:
 	 * For hyper-threaded CPUs these are shared.
 	 */
 	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 clear_mtrrs:
@@ -296,7 +296,7 @@ no_msr_11e:
 	cld
 	xorl	%eax, %eax
 	movl	$CACHE_AS_RAM_BASE, %edi
-	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
 	rep	stosl
 
 	/* Enable Cache-as-RAM mode by disabling cache. */
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 595b4df8b1..0a070b2e81 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -60,7 +60,7 @@ wait_for_sipi:
 	post_code(0x21)
 	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 clear_mtrrs:
@@ -116,7 +116,7 @@ clear_mtrrs:
        /* Clear the cache memory region. This will also fill up the cache */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
 	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 62f816acfd..cfa3b6b3bf 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -57,7 +57,7 @@ wait_for_sipi:
 	post_code(0x22)
 	/* Zero out all fixed range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 clear_mtrrs:
@@ -121,7 +121,7 @@ clear_var_mtrrs:
        /* Clear the cache memory region. This will also fill up the cache */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
 	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index f54c691b9a..2d469ffa03 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -55,7 +55,7 @@ wait_for_sipi:
 	post_code(0x21)
 	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 clear_mtrrs:
@@ -111,7 +111,7 @@ clear_mtrrs:
        /* Clear the cache memory region. This will also fill up the cache */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
 	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl
@@ -298,7 +298,7 @@ before_romstage:
 	cld
 	movl	$CONFIG_RAMBASE, %esi
 	movl	CBMEM_RESUME_BACKUP, %edi
-	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	movl	$HIGH_MEMORY_SAVE >> 2, %ecx
 	rep	movsl
 
 __acpi_resume_backup_done:
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index d7d932e817..271b7568d9 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -40,7 +40,7 @@ cache_as_ram:
 
 	/* Zero out all fixed range and variable range MTRRs. */
 	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 clear_mtrrs:
@@ -90,7 +90,7 @@ clear_mtrrs:
 	/* Clear the cache memory reagion. */
 	movl	$CACHE_AS_RAM_BASE, %esi
 	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
 	// movl	$0x23322332, %eax
 	xorl	%eax, %eax
 	rep	stosl