cpu/amd: Add initial support for AMD Socket G34 processors

Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11940
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

11 files changed, 204 insertions, 23 deletions

diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 8286b2a85b..3a02043848 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -5,6 +5,7 @@ source src/cpu/amd/socket_AM2/Kconfig
 source src/cpu/amd/socket_AM2r2/Kconfig
 source src/cpu/amd/socket_AM3/Kconfig
 source src/cpu/amd/socket_C32/Kconfig
+source src/cpu/amd/socket_G34/Kconfig
 source src/cpu/amd/socket_ASB2/Kconfig
 source src/cpu/amd/socket_F/Kconfig
 source src/cpu/amd/socket_F_1207/Kconfig
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index a73e25ff19..e532abab7d 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
+subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
 subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
 subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 96df3e7ff8..230d1aa65e 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,4 +1,5 @@
-/* 2005.6 by yhlu
+/* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * 2005.6 by yhlu
  * 2006.3 yhlu add copy data from CAR to ram
  */
 #include <string.h>
@@ -46,6 +47,15 @@ static void memset_(void *d, int val, size_t len)
 	memset(d, val, len);
 }
 
+static int memcmp_(void *d, const void *s, size_t len)
+{
+#if PRINTK_IN_CAR
+	printk(BIOS_SPEW, " Compare [%08x-%08x] with [%08x - %08x] ... ",
+		(u32) s, (u32) (s + len - 1), (u32) d, (u32) (d + len - 1));
+#endif
+	return memcmp(d, s, len);
+}
+
 static void prepare_romstage_ramstack(void *resume_backup_memory)
 {
 	size_t backup_top = backup_size();
@@ -110,6 +120,12 @@ void post_cache_as_ram(void)
 	memcpy_(migrated_car, &_car_data_start[0], car_size);
 	print_car_debug("Done\n");
 
+	print_car_debug("Verifying data integrity in RAM... ");
+	if (memcmp_(migrated_car, &_car_data_start[0], car_size) == 0)
+		print_car_debug("Done\n");
+	else
+		print_car_debug("FAILED\n");
+
 	/* New stack grows right below migrated_car. */
 	print_car_debug("Switching to use RAM as stack... ");
 	cache_as_ram_switch_stack(migrated_car);
@@ -128,6 +144,7 @@ void cache_as_ram_new_stack (void)
 	disable_cache_as_ram_bsp();
 
 	disable_cache();
+	/* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */
 	set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 	enable_cache();
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 4c72848986..8de6d25e6b 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -67,6 +68,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	u32 nb_cfg_54;
 	int i, j;
 	u32 ApicIdCoreIdSize;
+	uint8_t rev_gte_d = 0;
+	uint8_t dual_node = 0;
+	uint32_t f3xe8;
 
 	/* get_nodes define in ht_wrapper.c */
 	nodes = get_nodes();
@@ -81,6 +85,16 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	/* Assume that all node are same stepping, otherwise we can use use
 	   nb_cfg_54 from bsp for all nodes */
 	nb_cfg_54 = read_nb_cfg_54();
+	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
+
+	if (cpuid_eax(0x80000001) >= 0x8)
+		/* Revision D or later */
+		rev_gte_d = 1;
+
+	if (rev_gte_d)
+		 /* Check for dual node capability */
+		if (f3xe8 & 0x20000000)
+			dual_node = 1;
 
 	ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
 	if (ApicIdCoreIdSize) {
@@ -91,6 +105,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 
 	for (i = 0; i < nodes; i++) {
 		cores_found = get_core_num_in_bsp(i);
+		if (siblings > cores_found)
+			siblings = cores_found;
 
 		u32 jstart, jend;
 
@@ -107,9 +123,21 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 		}
 
 		for (j = jstart; j <= jend; j++) {
-			ap_apicid =
-			    i * (nb_cfg_54 ? (siblings + 1) : 1) +
-			    j * (nb_cfg_54 ? 1 : 64);
+			if (dual_node) {
+				ap_apicid = 0;
+				if (nb_cfg_54) {
+					ap_apicid |= ((i >> 1) & 0x3) << 4;			/* Node ID */
+					ap_apicid |= ((i & 0x1) * (siblings + 1)) + j;		/* Core ID */
+				} else {
+					ap_apicid |= i & 0x3;					/* Node ID */
+					ap_apicid |= (((i & 0x1) * (siblings + 1)) + j) << 4;	/* Core ID */
+				}
+			} else {
+				ap_apicid =
+				i * (nb_cfg_54 ? (siblings + 1) : 1) +
+				j * (nb_cfg_54 ? 1 : 64);
+			}
+
 
 #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
 #if !CONFIG_LIFT_BSP_APIC_ID
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 590b89d65e..b942c1a24a 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -153,6 +154,7 @@ static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
 	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
 	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100F91 },           /* HY-D1 */
 	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
 	{ 0, 0 },
 };
diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c
index a25e3a9bb6..12c45c92fe 100644
--- a/src/cpu/amd/model_10xxx/processor_name.c
+++ b/src/cpu/amd/model_10xxx/processor_name.c
@@ -157,6 +157,24 @@ static const struct str_s String2_socket_AM2[] = {
 	{0, 0, 0, NULL}
 };
 
+static const struct str_s String1_socket_G34[] = {
+	{0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"},
+	{0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"},
+	{0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "},
+	{0, 0, 0, NULL}
+};
+
+static const struct str_s String2_socket_G34[] = {
+	{0x00, 0x07, 0x00, " HE"},
+	{0x00, 0x07, 0x01, " SE"},
+	{0x00, 0x0B, 0x00, " HE"},
+	{0x00, 0x0B, 0x01, " SE"},
+	{0x00, 0x0B, 0x0F, ""},
+	{0x01, 0x07, 0x01, " QS"},
+	{0x01, 0x07, 0x02, " KS"},
+	{0, 0, 0, NULL}
+};
+
 static const struct str_s String1_socket_C32[] = {
 	{0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
 	{0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
@@ -240,6 +258,11 @@ int init_processor_name(void)
 		str = String1_socket_AM2;
 		str2 = String2_socket_AM2;
 		break;
+	case 3:		/* G34 */
+		str = String1_socket_G34;
+		str2 = String2_socket_G34;
+		str2_checkNC = 0;
+		break;
 	case 5:		/* C32 */
 		str = String1_socket_C32;
 		str2 = String2_socket_C32;
diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c
index c8637c9fa0..46ccdbd151 100644
--- a/src/cpu/amd/model_10xxx/ram_calc.c
+++ b/src/cpu/amd/model_10xxx/ram_calc.c
@@ -26,6 +26,7 @@
 
 #include "ram_calc.h"
 
+#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
 uint64_t get_uma_memory_size(uint64_t topmem)
 {
 	uint64_t uma_size = 0;
@@ -50,3 +51,4 @@ void *cbmem_top(void)
 
 	return (void *) topmem - get_uma_memory_size(topmem);
 }
+#endif
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index cf45196cf1..c5921dee7f 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -37,33 +38,71 @@ u32 get_initial_apicid(void)
 	return ((cpuid_ebx(1) >> 24) & 0xff);
 }
 
-//called by amd_siblings too
-#define CORE_ID_BIT 2
-#define NODE_ID_BIT 6
+/* Called by amd_siblings (ramstage) as well */
 struct node_core_id get_node_core_id(u32 nb_cfg_54)
 {
 	struct node_core_id id;
-	u32 core_id_bits;
+	uint8_t apicid;
+	uint8_t rev_gte_d = 0;
+	uint8_t dual_node = 0;
+	uint32_t f3xe8;
 
-	u32 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
-	if(ApicIdCoreIdSize) {
-		core_id_bits = ApicIdCoreIdSize;
-	} else {
-		core_id_bits = CORE_ID_BIT; //quad core
-	}
+#ifdef __PRE_RAM__
+	f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
+#else
+	f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
+#endif
+
+	if (cpuid_eax(0x80000001) >= 0x8)
+		/* Revision D or later */
+		rev_gte_d = 1;
 
-	// get the apicid via cpuid(1) ebx[31:24]
+	if (rev_gte_d)
+		 /* Check for dual node capability */
+		if (f3xe8 & 0x20000000)
+			dual_node = 1;
+
+	/* Get the apicid via cpuid(1) ebx[31:24]
+	 * The apicid format varies based on processor revision
+	 */
+	apicid = (cpuid_ebx(1) >> 24) & 0xff;
 	if( nb_cfg_54) {
-		// when NB_CFG[54] is set, nodeid = ebx[31:26], coreid = ebx[25:24]
-		id.coreid = (cpuid_ebx(1) >> 24) & 0xff;
-		id.nodeid = (id.coreid>>core_id_bits);
-		id.coreid &= ((1<<core_id_bits)-1);
+		if (rev_gte_d && dual_node) {
+			id.coreid = apicid & 0xf;
+			id.nodeid = (apicid & 0x30) >> 4;
+		} else if (rev_gte_d && !dual_node) {
+			id.coreid = apicid & 0x7;
+			id.nodeid = (apicid & 0x38) >> 3;
+		} else {
+			id.coreid = apicid & 0x3;
+			id.nodeid = (apicid & 0x1c) >> 2;
+		}
 	} else {
-		// when NB_CFG[54] is clear, nodeid = ebx[29:24], coreid = ebx[31:30]
-		id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
-		id.coreid = (id.nodeid>>NODE_ID_BIT);
-		id.nodeid &= ((1<<NODE_ID_BIT)-1);
+		if (rev_gte_d && dual_node) {
+			id.coreid = (apicid & 0xf0) >> 4;
+			id.nodeid = apicid & 0x3;
+		} else if (rev_gte_d && !dual_node) {
+			id.coreid = (apicid & 0xe0) >> 5;
+			id.nodeid = apicid & 0x7;
+		} else {
+			id.coreid = (apicid & 0x60) >> 5;
+			id.nodeid = apicid & 0x7;
+		}
 	}
+
+	if (rev_gte_d && dual_node) {
+		/* Coreboot expects each separate processor die to be on a different nodeid.
+		 * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed...
+		 */
+		uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1;
+
+		id.nodeid = id.nodeid * 2;
+		if (id.coreid >= core_count) {
+			id.nodeid += 1;
+			id.coreid = id.coreid - core_count;
+		}
+	}
+
 	return id;
 }
 
diff --git a/src/cpu/amd/socket_G34/Kconfig b/src/cpu/amd/socket_G34/Kconfig
new file mode 100644
index 0000000000..abc9726c78
--- /dev/null
+++ b/src/cpu/amd/socket_G34/Kconfig
@@ -0,0 +1,29 @@
+config CPU_AMD_SOCKET_G34_NON_AGESA
+	bool
+	select CPU_AMD_MODEL_10XXX
+	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_SOCKET_G34_NON_AGESA
+
+config CPU_SOCKET_TYPE
+	hex
+	default 0x15
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+
+config CBB
+	hex
+	default 0x0
+
+config CDB
+	hex
+	default 0x18
+
+config XIP_ROM_SIZE
+	hex
+	default 0x80000
+
+endif
diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc
new file mode 100644
index 0000000000..a8e1333d9b
--- /dev/null
+++ b/src/cpu/amd/socket_G34/Makefile.inc
@@ -0,0 +1,14 @@
+ramstage-y += socket_G34.c
+subdirs-y += ../model_10xxx
+subdirs-y += ../quadcore
+subdirs-y += ../mtrr
+subdirs-y += ../microcode
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/pae
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../smm
+
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c
new file mode 100644
index 0000000000..90f7b8c44f
--- /dev/null
+++ b/src/cpu/amd/socket_G34/socket_G34.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations cpu_amd_socket_G34_ops = {
+	CHIP_NAME("socket G34")
+};