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authorElyes HAOUAS <ehaouas@noos.fr>2021-01-05 14:38:57 +0100
committerArthur Heymans <arthur@aheymans.xyz>2021-01-21 09:08:14 +0000
commit985821c4f2feda41ed2d1ab83f6ae7b8f15197bd (patch)
tree53af8c6c11a980690639e87e60cf5dc139a2baa0 /src/cpu
parent083702c32ed2e70fd49ec7b02a79731173970a6d (diff)
cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE". It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets should have at least 256K L2 cache. That is plenty for XIP RO cache of bootblock + romstage and a 32K CAR. Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/socket_LGA775/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8db932ce58..537a0d1c5f 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -17,7 +17,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_SIZE
hex
- default 0x4000 # 16 kB
+ default 0x8000 # 32 kB
config DCACHE_BSP_STACK_SIZE
hex