Ignore RAMTOP for MTRRs

Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.

With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.

Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

12 files changed, 18 insertions, 18 deletions

diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 5f486f2fea..3a60b8d06c 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -75,11 +75,11 @@ static void set_resume_cache(void)
 	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
 	wrmsr(SYSCFG_MSR, msr);
 
-	/* Enable caching for 0 - coreboot ram using variable mtrr */
+	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
 	msr.lo = 0 | MTRR_TYPE_WRBACK;
 	msr.hi = 0;
 	wrmsr(MTRR_PHYS_BASE(0), msr);
-	msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
+	msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
 	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
 	wrmsr(MTRR_PHYS_MASK(0), msr);
 
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 0a59696b56..1880ccb441 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -175,8 +175,8 @@ void cache_as_ram_new_stack (void)
 	disable_cache_as_ram_bsp();
 
 	disable_cache();
-	/* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */
-	set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
+	set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
 	enable_cache();
 
 	if (acpi_is_wakeup_s3()) {
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index c1ff24042d..0edded2b8c 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -519,7 +519,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 
 		/* AP is ready, configure MTRRs and go to sleep */
 		if (set_mtrrs)
-			set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+			set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
 
 		printk(BIOS_DEBUG, "Disabling CAR on AP %02x\n", apicid);
 		if (is_fam15h()) {
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 8968e7e0be..51e1b7c849 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -326,7 +326,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 			       apicid);
 		}
 		lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44);	// bsp can not check it before stop_this_cpu
-		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
+		set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
 #if CONFIG_K8_REV_F_SUPPORT
 #if CONFIG_MEM_TRAIN_SEQ == 1
 		train_ram_on_node(id.nodeid, id.coreid, sysinfo,
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index b1e599acb1..cf0b08a04c 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -173,12 +173,12 @@ static void set_init_ecc_mtrrs(void)
 		wrmsr(MTRR_PHYS_MASK(i), zero);
 	}
 
-	/* Write back cache the first 1MB */
+	/* Write back cache from 0x0 to CACHE_TMP_RAMTOP. */
 	msr.hi = 0x00000000;
 	msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
 	wrmsr(MTRR_PHYS_BASE(0), msr);
 	msr.hi = 0x000000ff;
-	msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
+	msr.lo = ~((CACHE_TMP_RAMTOP) - 1) | 0x800;
 	wrmsr(MTRR_PHYS_MASK(0), msr);
 
 	/* Set the default type to write combining */
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
index 53172d48f6..b6d363377a 100644
--- a/src/cpu/amd/pi/s3_resume.c
+++ b/src/cpu/amd/pi/s3_resume.c
@@ -271,11 +271,11 @@ static void set_resume_cache(void)
 	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
 	wrmsr(SYSCFG_MSR, msr);
 
-	/* Enable caching for 0 - coreboot ram using variable mtrr */
+	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
 	msr.lo = 0 | MTRR_TYPE_WRBACK;
 	msr.hi = 0;
 	wrmsr(MTRR_PHYS_BASE(0), msr);
-	msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
+	msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
 	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
 	wrmsr(MTRR_PHYS_MASK(0), msr);
 
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 1e21d9dc6d..095b9b6cda 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -388,7 +388,7 @@ no_msr_11e:
 	wrmsr
 	movl	$MTRR_PHYS_MASK(0), %ecx
 	rdmsr
-	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
 
 #if CACHE_ROM_SIZE
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index b8ce5d6d43..0e8fd09837 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -119,9 +119,9 @@ static void *setup_romstage_stack_after_car(void)
 	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 	num_mtrrs++;
 
-	/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+	slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
 	slot = stack_push(slot, 0); /* upper base */
 	slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 51af5c69d2..e6d95d572a 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -233,7 +233,7 @@ before_romstage:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRR_PHYS_MASK(0), %ecx
-	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 0dc3cab1dd..a1f5cc9d80 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -243,7 +243,7 @@ before_romstage:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRR_PHYS_MASK(0), %ecx
-	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 79383e163f..6b80e7ae7b 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -182,7 +182,7 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRR_PHYS_MASK(0), %ecx
-	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 2f61b9138a..8d02e5d2ec 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -225,7 +225,7 @@ testok:
 	movl	$(MTRR_DEF_TYPE_EN), %eax
 	wrmsr
 
-	/* Enable caching for 0..CONFIG_RAMTOP. */
+	/* Enable caching for 0..CACHE_TMP_RAMTOP. */
 	movl	$MTRR_PHYS_BASE(0), %ecx
 	xorl	%edx, %edx
 	movl	$(0x0 | MTRR_TYPE_WRBACK), %eax
@@ -233,7 +233,7 @@ testok:
 
 	movl	$MTRR_PHYS_MASK(0), %ecx
 	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
-	movl	$(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
 
 	/* Cache XIP_ROM area to speedup coreboot code. */