diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-25 15:07:34 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:43:30 +0100 |
| commit | 38508a0ff1b0bcdadc779ae8a8a422638d4612d9 (patch) | |
| tree | 3600cae33a8bc3c1fa6952c25b43453e4dd0e351 /src/cpu | |
| parent | eb2f6fff3265b5be87e2dfc9e69ad465c742ec8c (diff) | |
cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
There were numerous issues surrounding AMD ECC initialization on
Family 15h processors due to the incomplete derivation from Family
10h MCT code. Bring the Family 15h ECC initialization and supporting
setup code in line with the BKDG recommendations.
Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12003
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 4 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 3295ccc3b1..cbb1e39854 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -359,12 +359,16 @@ clear_fixed_var_mtrr_out: simplemask CacheSize, 0 wrmsr + jmp_if_fam15h(fam15_skip_dram_mtrr_setup) + /* Enable memory access for first MBs using top_mem. */ movl $TOP_MEM, %ecx xorl %edx, %edx movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr +fam15_skip_dram_mtrr_setup: + #if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c9dca765c4..e4721a43f3 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -313,6 +313,22 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) msr = rdmsr(BU_CFG2); msr.lo &= ~(1 << ClLinesToNbDis); wrmsr(BU_CFG2, msr); + } else { + /* Family 15h or later + * DRAM setup is delayed on Fam15 in order to prevent + * any DRAM access before ECC check bits are initialized. + * Each core also needs to have its initial DRAM map initialized + * before it is put to sleep, otherwise it will fail to wake + * in ramstage. To meet both of these goals, delay DRAM map + * setup until the last possible moment, where speculative + * memory access is highly unlikely before core halt... + */ + if (!skip_sharedc_config) { + /* Enable memory access for first MBs using top_mem */ + msr.hi = 0; + msr.lo = (CONFIG_RAMTOP + TOP_MEM_MASK) & (~TOP_MEM_MASK); + wrmsr(TOP_MEM, msr); + } } disable_cache_as_ram(skip_sharedc_config); // inline |