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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-28 15:00:39 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-29 20:19:52 +0000
commit3054a1927983ef07cbc147ba776ea5d990571bdd (patch)
tree87a6860bc1846b912661ed1eb4f0edd1c87a1453 /src/cpu
parent4ea47c32b01d1604ec2b4d0b40b433454e62c520 (diff)
soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay
Correct the mask for the power cycle delay from 0xff to 0x1f, to represent the actual maximum value according to Intel graphics PRM for Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c. Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions