diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2005-01-15 04:12:27 +0000 |
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committer | Yinghai Lu <yinghailu@gmail.com> | 2005-01-15 04:12:27 +0000 |
commit | 1d6b46060c303f7902ec414f544984af019b9908 (patch) | |
tree | 09034606cc822216719b0646df6b987bdc437d0c /src/cpu | |
parent | e562738f8c80ea15ffa28e63c17fdd3c82e876af (diff) |
can not enable cache for ram in auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/amd/mtrr/amd_earlymtrr.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c index 6606a92e9b..d0647ac135 100644 --- a/src/cpu/amd/mtrr/amd_earlymtrr.c +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -40,23 +40,6 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs) msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); wrmsr(TOP_MEM, msr); - /* Enable caching for 0 - 1MB using variable mtrr */ -#if 0 - set_var_mtrr(0, 0x00000000, (CONFIG_LB_MEM_TOPK << 10), MTRR_TYPE_WRBACK); -#else - msr = rdmsr(0x200); - msr.hi = 0x00000000; - msr.lo &= 0x00000f00; - msr.lo |= 0x00000000 | MTRR_TYPE_WRBACK; - wrmsr(0x200, msr); - - msr = rdmsr(0x201); - msr.hi = 0x0000000f; - msr.lo &= 0x000007ff; - msr.lo |= (~((CONFIG_LB_MEM_TOPK << 10) - 1)) | 0x800; - wrmsr(0x201, msr); -#endif - #if defined(XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. |