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| author | Jeremy Soller <jeremy@system76.com> | 2021-08-12 10:49:58 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-24 14:49:33 +0000 |
| commit | bc071feec18fb7feffbcacde74d101348c65e98e (patch) | |
| tree | 3000fdc6a32fe37f7dc6b01bc9132cf8b3cdcdc9 /src/cpu/x86 | |
| parent | 83d795c45b602ed1736e80871b2bd5cd2ccf7490 (diff) | |
soc/intel/tigerlake: Add TGL-H PEG ports
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/cpu/x86')
0 files changed, 0 insertions, 0 deletions