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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-21 09:32:45 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-16 03:42:21 +0000 |
| commit | 09a6d633aeed5986bb503482ebdf28fc1851c631 (patch) | |
| tree | 1f145c9f6bc0919070f0a38ad6b94c1d8dc55686 /src/cpu/x86 | |
| parent | a5061f8f5772e59725c8e89e02b9dff10735e915 (diff) | |
cpu/x86/mp_init: Support both xapic and x2apic with common code
Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT,
specifically for (obsolete) Init Level De-assert.
Level LAPIC_INT_ASSERT is required to be set for all other delivery
modes other than LAPIC_DM_INIT.
This reverts the two above changes that X2APIC mode support introduced
to the IPI for LAPIC_DM_SMI.
Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/mp_init.c | 40 |
1 files changed, 10 insertions, 30 deletions
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index ad45ee96f9..cd6d8ca63d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -435,27 +435,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); - if (is_x2apic_mode()) { - x2apic_send_ipi(LAPIC_DM_INIT | LAPIC_INT_LEVELTRIG | - LAPIC_INT_ASSERT | LAPIC_DEST_ALLBUT, 0); - mdelay(10); - x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG | - LAPIC_DEST_ALLBUT | sipi_vector, 0); - - /* Wait for CPUs to check in up to 200 us. */ - wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); - - x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG | - LAPIC_DEST_ALLBUT | sipi_vector, 0); - - /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { - printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", - atomic_read(num_aps), ap_count); - return -1; - } - return 0; - } + int x2apic_mode = is_x2apic_mode(); + printk(BIOS_DEBUG, "Starting CPUs in %s mode\n", x2apic_mode ? "x2apic" : "xapic"); if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); @@ -671,11 +652,6 @@ static void mp_initialize_cpu(void) void smm_initiate_relocation_parallel(void) { - if (is_x2apic_mode()) { - x2apic_send_ipi(LAPIC_DM_SMI | LAPIC_INT_LEVELTRIG, lapicid()); - return; - } - if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { @@ -686,10 +662,14 @@ void smm_initiate_relocation_parallel(void) } lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); - if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) - printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); - else - printk(BIOS_DEBUG, "Relocation complete.\n"); + + if (lapic_busy()) { + if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) { + printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); + return; + } + } + printk(BIOS_DEBUG, "Relocation complete.\n"); } DECLARE_SPIN_LOCK(smm_relocation_lock); |