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authorStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-13 00:13:50 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-13 00:27:07 +0200
commit3a09179f462ad3f6111c7b8ebbad7d78534f9234 (patch)
treeb854e11a926e555a4ade85950846b8cdea0ce56b /src/cpu/x86
parent0210119b4b95e84f954cfd6dc11aafbc187421af (diff)
Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2 Reviewed-on: http://review.coreboot.org/3443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/smm/smmrelocate.S5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index b42ac5da60..16d4b9fde0 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -37,8 +37,6 @@
#include "../../../southbridge/intel/sch/sch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
#include "../../../southbridge/intel/bd82x6x/pch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK
-#include "../../../southbridge/intel/ibexpeak/pch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
#else
@@ -50,9 +48,6 @@
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM
-#include <northbridge/intel/nehalem/nehalem.h>
-#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else
#error "Northbridge must define TSEG_BAR."
#endif